Superconducting Technology Assessment - nitrd

ground plane may be located either below the trilayer or, less
often, on the top. Optical photolithography (either g-line or
i-line) is used to transfer the mask design to the photoresist
in most cases. E-beam lithography is also used to write the
smallest features ( 1 m) in some processes. The features
are then patterned by a variety of methods including etching
by reactive ion etching (RIE) or inductively coupled plasma
(ICP) etching, anodization, and liftoff. The integrated circuit
fabrication processes are discussed in more detail below.
B. Fabrication Challenges
The challenges in the fabrication of superconductor
integrated circuits fall broadly into two categories: improving
parametric performance and minimizing process-induced
defects. Parametric performance involves the targeting
of important device parameters and minimizing device variation,
both on a local and global scale. We discuss this in
more detail in Section V. Process defects include unwanted
contamination, lack of integrity in wiring or dielectrics,
etc., and are typically represented as defect density. Even
for modest feature sizes (i.e., 1 m), defect density is an
important consideration and care must be taken to minimize
contributions from the environment, while working to reduce
contributions from the process itself. These challenges
are similar to those faced by the semiconductor industry,
because many of the tools, methods, and materials are
similar. We have adopted solutions already developed by
the semiconductor industry and adapted them to the specific
needs of superconductor integrated circuit manufacturing.
For example, class 100 to class 10 clean rooms, depending
on the level of integration, and clean room process tools,
such as load-locked vacuum systems and automated wafer
handling, are used to minimize defects.
Much work has been done over the past decade to minimize
process-induced defects. Process improvements to
address dielectric integrity included the use of sputtered
SiO as a replacement for evaporated SiO, which helped
to reduce pinhole density in the interlevel dielectric and
improved step coverage of the overlying metal layer. Implementation
of bias-sputtered SiO was another improvement
that further improved dielectric integrity and improved metal
step coverage [41]. Another approach to improved step coverage
is the use of electron cyclotron resonance (ECR)
plasma-enhanced chemical vapor deposition (PECVD)
SiO , which provides a collateral benefit of improved junction
characteristics [20], [42].
Another challenge in superconductor integrated circuit
fabrication is addressing material properties limitations for
materials such as niobium nitride. Unlike niobium in which
the Nb/Al-AlO /Nb trilayer is relatively straightforward
to produce with good uniformity, the tunnel barrier for
niobium nitride is more challenging. Sputter-deposited
MgO and AlN are the typical material choices for tunnel
barriers [37], [43]. Controlling the thickness (on the order
of 1 nm) and uniformity (to better than 0.01 nm!) of an
ultrathin barrier such as MgO is difficult by conventional
sputter deposition techniques. Accurate targeting of junction
becomes very difficult because is an exponential
Table 4
Nb and Al Sputter Deposition Parameters
function of the tunnel barrier thickness. In situ oxidation of
deposited Mg is another method that has been explored with
encouraging results [44]. The potential advantage of this
approach is a uniform barrier thickness across the wafer and
more controllable targeting. Although robust to chemical
damage during processing, niobium nitride poses other difficulties
for integrated circuit fabrication because of its large
penetration depth and columnar growth [45], [46]. In order
to overcome this, layer thicknesses are increased, causing
step coverage problems. Innovative circuit design can help
mitigate the problem, but the real solution is planarization
and migration to other materials such as NbTiN, which has a
much lower penetration depth, and so it can be made thinner
[47]. Planarization, as discussed in Section IV, has been used
successfully in niobium-based technology and could readily
be adapted to niobium nitride to mitigate some of the step
coverage problems.
III. JUNCTION FABRICATION
A. Nb/Al-AlOx/Nb Trilayer Deposition
Fabrication of large numbers of Josephson junctions
with predictable and uniform electrical properties is the
key first step in the development of an advanced superconductor
integrated circuit process. Fabrication of high quality
Josephson junctions starts from an in situ deposited trilayer
of Nb/Al-AlO /Nb. The trilayer is patterned using standard
lithographic and RIE processes to define the niobium base
and counterelectrodes of the Josephson junction. This has
been the preferred method since the first demonstration
of Nb/Al-AlO /Nb trilayer process [48]. Many details of
trilayer deposition processes and basic junction fabrication
can be found elsewhere [49]–[52].
The trilayer deposition is performed in a dedicated process
tool (sputter deposition system) designed for this process,
which is standard practice in the industry. The process
tool generally consists of a multigun, sputter deposition
chamber, oxidation chamber, glow discharge chamber, and
a load lock chamber to transfer wafers in and out of the
process tool. The process tool should be capable of maintaining
base pressures in the low 10 torr range. In the
trilayer deposition process used at NGST, the niobium base
electrode and aluminum tunnel barrier metals (Nb/Al) are
sputter-deposited sequentially in the deposition chamber.
1520 PROCEEDINGS OF THE IEEE, VOL. 92, NO. 10, OCTOBER 2004