Elektronika 2009-11.pdf - Instytut Systemów Elektronicznych

Example of concurrent resource
allocation and task scheduling
Let us discuss a simple example for management of multiprocessors
system with fault tolerant where assuming that
tasks (with applications requirements) of the system are given
by the tasks graph. The digraph presented in Fig. 4 defines
the precedence constraints of tasks of the modeled system.
Fig. 4. Task digraph Rys. 4. Graf zadań
The optimality criterion is the minimum of the task processing
time, i.e. a minimum of the task schedule length. An
additional criterion is cost, related to the number of used resources.
We shall define constraints of the resources available.
Compilation of all operations [6] of the system, the
characteristics of available resources and database (with resource
allocations in the past) give us the times of task processing
(we assume conventional time units).
We assume the following times of individual tasks for a
standard processor: t 0 = 3, t 1 = 2, t 2 = 2, t 3 = 1, t 4 = 3, t 5 = 3,
t 6 = 4, t 7 = 3, t 8 = 1, t 9 = 1. Let us assume that the cost of one
executive module is:
C = C P + i • C M (1)
where: C P - processor cost, C M - memory module cost,
i - number of memory modules.
The requirements for realizing all operations of the system
shall be specified as follows:
• the acceptable deadline for performing all tasks without any
delays is 13 time units;
• it is necessary to perform task T 6 indivisibly in time;
• it is necessary to provide a deadline for task T 6 equal
9 time units;
• the desirable deadline for performing all tasks without any
delays is at most 10 time units.
The cost of the system should be as low as possible, and
the structure conformable to the fault tolerance system model
with two-processor testing tasks. We shall denote processor
testing tasks by T gh , if processor P g is testing processor P h .
The first step of the planning has to determine the number
of parallel processors needed for the execution of all requirements
and constraints. The structure of four parallel
processors shall be assumed. This structure of a fault tolerance
the system satisfying the requirement “1.” is shown in
Fig. 5 (variant a).
Fig. 5. Structures of fault tolerance multiprocessor system
Rys. 5. Struktury wieloprocesorowe z tolerancją uszkodzeń
The optimum tasks schedule for such architecture is presented
in Table 1. Taking into account the requirement “2.”,
a correction is done to the task schedule. The system structure
and costs remain unchanged.
The next requirement “3.” is reflected in a corrected
schedule presented in Table 1. Please notice that the system
architecture and costs remain unchanged. Only tasks schedule
is modified.
In order to carry out the requirement “4.”, a change of the
system structure is necessary. Two variants of the structure
shall be proposed. The first structure consists of five identical
parallel processors, with two-processor testing tasks Fig. 2 -
variant b). Task schedule in such structure is depicted in
Table 2 (variant b). In the second variant, a specialized module
(ASIC - if is available) is applied that can perform the
Tabl. 1. Schedule of task in a four-processors (structure: variant a) satisfying
the requirement “1.”= (1) and “1.”+”2.”+”3.” = (3) (X - idle time)
Tab. 1. Uszeregowanie zadań na 4 procesorach (struktura: wariant a)
zgodnie z wymaganiami ”1.” = (1) i “1.”+”2.”+”3.” = (3) (X - czas przestoju
procesora)
time P1 (1) P2 (1) P3 (1) P4 (1) P1 (3) P2 (3) P3 (3) P4 (3)
1 T12 T12 T0 X T12 T12 T0 X
2 T0 T23 T23 X T0 T23 T23 X
3 T0 X T34 T34 T0 X T34 T34
4 T13 T1 T13 T2 T13 T1 T13 T2
5 T1 T24 T2 T24 T1 T24 T2 T24
6 T31 T4 T31 T3 T31 T6 T31 T3
7 T14 T4 T5 T14 T14 T6 T5 T14
8 T21 T21 T4 T6 T21 T21 T4 T6
9 T7 T32 T32 T6 T7 T32 T32 T6
10 T41 T6 T5 T41 T41 T4 T5 T41
11 T7 T42 T5 T42 T4 T42 T5 T42
12 T6 T8 T43 T43 T6 T8 T43 T43
13 T12 T12 T7 T9 T12 T12 T7 T9
Tabl. 2. Schedule of tasks in a five-processors (structure: variant b)
and in a three-processors with specialized ASIC processor (structure:
variant c) satisfying the requirements “1.”+”2.”+”3.”+”4.” (X - idle time)
Tab. 2. Uszeregowanie zadań na 5 procesorach (struktura: wariant b)
i na 3 procesorach z procesorem specjalizowanym ASIC (struktura
wariant c) zgodnie z wymaganiami “1.”+”2.”+”3.” +”4.” (X - czas przestoju
procesora)
time P1 (b) P2 (b) P3 (b) P4 (b) P5 (b) P1 (c) P2 (c) P3 (c) ASIC (c)
1 T12 T12 X T0 X T12 T12 X T0
2 X T23 T23 T0 X T2 T23 T23 X
3 X X T34 T34 T0 T13 T2 T13 X
4 T1 T2 T6 T45 T45 T21 T21 T6 T4
5 T13 T2 T13 T1 T6 T1 T32 T32 T6
6 T3 T24 T5 T24 T6 T31 T1 T31 X
7 T4 T5 T35 T6 T35 T12 T12 T3 T5
8 T14 T5 T4 T14 T7 T8 T23 T23 T7
9 T9 T25 T4 T7 T25 T13 T13 T9 X
10 T15 T8 T9 T7 T15 X X X X
11 T21 T21 X X X X X X X
12 X T32 T32 X X X X X X
13 X X T43 T43 X X X X X
40 ELEKTRONIKA 11/2009