1Gb: x8, x16 Automotive DDR2 SDRAM - Micron

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Figure 63: WRITE – DM Operation CK# CK CKE Command Address A10 Bank select DQS, DQS# DQ 7 DM T0 T1 T2 T3 T4 T5 T6 T6n T7 T7n T8 NOP 1 ACT RA tCK tCH tCL NOP 1 RA Col n Bank x tRCD WRITE2 NOP1 NOP1 NOP1 NOP1 NOP1 NOP1 NOP1 AL = 1 WL = 2 3 Bank x WL ±tDQSS (NOM) 1Gb: x8, x16 Automotive DDR2 SDRAM WRITE tWPRE DI n tRAS 6 tDQSL tDQSH tWPST T9 T10 T11 tWR 5 Transitioning Data PRE All banks One bank Bank x 4 tRPA Don’t Care Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid at these times. 2. BL = 4, AL = 1, and WL = 2 in the case shown. 3. Disable auto precharge. 4. “Don’t Care” if A10 is HIGH at T11. 5. t WR starts at the end of the data burst regardless of the data mask condition. 6. Subsequent rising DQS signals must align to the clock within t DQSS. 7. DI n = data-in for column n; subsequent elements are applied in the programmed order. 8. t DSH is applicable during t DQSS (MIN) and is referenced from CK T6 or T7. 9. t DSS is applicable during t DQSS (MAX) and is referenced from CK T7 or T8. PDF: 09005aef840eff89 1gbddr2_ait_aat.pdf – Rev. C 7/11 EN 108 Micron Technology, Inc. reserves the right to change products or specifications without notice. � 2010 Micron Technology, Inc. All rights reserved.
Figure 64: Data Input Timing PRECHARGE CK# CK DQS DQS# DQ DM T0 T1 T1n T2 T2n T3 T3n T4 WL - t DQSS (NOM) t WPRE DI 1Gb: x8, x16 Automotive DDR2 SDRAM PRECHARGE tDSH 1 tDSS 2 tDSH 1 tDSS 2 3 t DQSL t DQSH t WPST Transitioning Data Don’t Care Notes: 1. t DSH (MIN) generally occurs during t DQSS (MIN). 2. t DSS (MIN) generally occurs during t DQSS (MAX). 3. Subsequent rising DQS signals must align to the clock within t DQSS. 4. WRITE command issued at T0. 5. For x16, LDQS controls the lower byte and UDQS controls the upper byte. 6. WRITE command with WL = 2 (CL = 3, AL = 0) issued at T0. Precharge can be initiated by either a manual PRECHARGE command or by an autoprecharge in conjunction with either a READ or WRITE command. Precharge will deactivate the open row in a particular bank or the open row in all banks. The PRECHARGE operation is shown in the previous READ and WRITE operation sections. During a manual PRECHARGE command, the A10 input determines whether one or all banks are to be precharged. In the case where only one bank is to be precharged, bank address inputs determine the bank to be precharged. When all banks are to be precharged, the bank address inputs are treated as “Don’t Care.” Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. When a single-bank PRE- CHARGE command is issued, tRP timing applies. When the PRECHARGE (ALL) command is issued, tRPA timing applies, regardless of the number of banks opened. PDF: 09005aef840eff89 1gbddr2_ait_aat.pdf – Rev. C 7/11 EN 109 Micron Technology, Inc. reserves the right to change products or specifications without notice. � 2010 Micron Technology, Inc. All rights reserved.
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Automotive DDR2 SDRAM MT47H128M8 -
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1Gb: x8, x16 Automotive DDR2 SDRAM
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Functional Description Automotive I
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Functional Block Diagrams The DDR2
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Ball Assignments and Descriptions F
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Table 3: FBGA 84-Ball - x16 and 60-
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Packaging Package Dimensions Figure
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FBGA Package Capacitance Table 4: I
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Table 6: Temperature Limits Paramet
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I DD7 Conditions The detailed timin
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Table 10: DDR2 I DD Specifications
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PDF: 09005aef840eff89 Micron Techno
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AC and DC Operating Conditions Tabl
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Input Electrical Characteristics an
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Table 19: Output Characteristics Pa
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Figure 15: Full Strength Pull-Up Ch
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Figure 17: Reduced Strength Pull-Up
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AC Overshoot/Undershoot Specificati
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Input Slew Rate Derating 1Gb: x8, x
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Page 57 and 58: Figure 23: Nominal Slew Rate for t
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Page 61 and 62: Table 34: Single-Ended DQS Slew Rat
Page 63 and 64: Figure 27: Nominal Slew Rate for t
Page 65 and 66: Figure 31: AC Input Test Signal Wav
Page 67 and 68: 6. Bank addresses (BA) determine wh
Page 69 and 70: Table 38: Truth Table - Current Sta
Page 71 and 72: NO OPERATION (NOP) LOAD MODE (LM) A
Page 73 and 74: Burst Length Figure 33: MR Definiti
Page 75 and 76: Write Recovery Power-Down Mode 1Gb:
Page 77 and 78: Extended Mode Register (EMR) Figure
Page 79 and 80: On-Die Termination (ODT) ODT effect
Page 81 and 82: Extended Mode Register 2 (EMR2) Fig
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Page 85 and 86: 1Gb: x8, x16 Automotive DDR2 SDRAM
Page 87 and 88: Figure 42: Multibank Activate Restr
Page 89 and 90: Figure 43: READ Latency CK# CK Comm
Page 91 and 92: Figure 45: Nonconsecutive READ Burs
Page 93 and 94: Figure 48: READ-to-PRECHARGE - BL =
Page 95 and 96: Figure 50: Bank Read - Without Auto
Page 97 and 98: Figure 52: x4, x8 Data Output Timin
Page 99 and 100: Figure 54: Data Output Timing - t A
Page 101 and 102: Figure 55: Write Burst CK# CK Comma
Page 103 and 104: Figure 58: WRITE Interrupted by WRI
Page 105 and 106: Figure 60: WRITE-to-PRECHARGE CK# C
Page 107: Figure 62: Bank Write - with Auto P
Page 111 and 112: SELF REFRESH 1Gb: x8, x16 Automotiv
Page 113 and 114: Power-Down Mode 1Gb: x8, x16 Automo
Page 115 and 116: Table 43: Truth Table - CKE 1Gb: x8
Page 117 and 118: Figure 70: WRITE-to-Power-Down or S
Page 119 and 120: Figure 74: PRECHARGE Command-to-Pow
Page 121 and 122: Reset CKE Low Anytime 1Gb: x8, x16
Page 123 and 124: ODT Timing 1Gb: x8, x16 Automotive
Page 125 and 126: MRS Command to ODT Update Delay Dur
Page 127 and 128: Figure 83: ODT Turn-On Timing When
Page 129: Figure 85: ODT Turn-On Timing When
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1Gb: x8, x16 Automotive DDR2 SDRAM - Micron

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