1Gb: x8, x16 Automotive DDR2 SDRAM - Micron

Figure 64: Data Input Timing
PRECHARGE
CK#
CK
DQS
DQS#
DQ
DM
T0 T1 T1n T2 T2n T3 T3n T4
WL - t DQSS (NOM)
t WPRE
DI
1Gb: x8, x16 Automotive DDR2 SDRAM
PRECHARGE
tDSH 1 tDSS 2 tDSH 1 tDSS 2
3
t DQSL
t DQSH t WPST
Transitioning Data
Don’t Care
Notes: 1. t DSH (MIN) generally occurs during t DQSS (MIN).
2. t DSS (MIN) generally occurs during t DQSS (MAX).
3. Subsequent rising DQS signals must align to the clock within t DQSS.
4. WRITE command issued at T0.
5. For x16, LDQS controls the lower byte and UDQS controls the upper byte.
6. WRITE command with WL = 2 (CL = 3, AL = 0) issued at T0.
Precharge can be initiated by either a manual PRECHARGE command or by an autoprecharge
in conjunction with either a READ or WRITE command. Precharge will deactivate
the open row in a particular bank or the open row in all banks. The PRECHARGE
operation is shown in the previous READ and WRITE operation sections.
During a manual PRECHARGE command, the A10 input determines whether one or all
banks are to be precharged. In the case where only one bank is to be precharged, bank
address inputs determine the bank to be precharged. When all banks are to be precharged,
the bank address inputs are treated as “Don’t Care.”
Once a bank has been precharged, it is in the idle state and must be activated prior to
any READ or WRITE commands being issued to that bank. When a single-bank PRE-
CHARGE command is issued, tRP timing applies. When the PRECHARGE (ALL) command
is issued, tRPA timing applies, regardless of the number of banks opened.
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1gbddr2_ait_aat.pdf – Rev. C 7/11 EN 109 Micron Technology, Inc. reserves the right to change products or specifications without notice.
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