1Gb: x8, x16 Automotive DDR2 SDRAM - Micron

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Table 27: AC Input Test Conditions Parameter Symbol Min Max Units Notes Input setup timing measurement reference level address balls, bank address balls, CS#, RAS#, CAS#, WE#, ODT, DM, UDM, LDM, and CKE VRS See Note 2 1, 2, 3, 4 Input hold timing measurement reference level address balls, bank address balls, CS#, RAS#, CAS#, WE#, ODT, DM, UDM, LDM, and CKE Input timing measurement reference level (single-ended) DQS for x4, x8; UDQS, LDQS for x16 Input timing measurement reference level (differential) CK, CK# for x4, x8, x16; DQS, DQS# for x4, x8; RDQS, RDQS# for x8; UDQS, UDQS#, LDQS, LDQS# for x16 1Gb: x8, x16 Automotive DDR2 SDRAM AC Overshoot/Undershoot Specification V RH See Note 5 1, 3, 4, 5 V REF(DC) V DDQ × 0.49 V DDQ × 0.51 V 1, 3, 4, 6 V RD V IX(AC) V 1, 3, 7, 8, 9 Notes: 1. All voltages referenced to V SS. 2. Input waveform setup timing ( t IS b) is referenced from the input signal crossing at the V IH(AC) level for a rising signal and V IL(AC) for a falling signal applied to the device under test, as shown in Figure 29 (page 64). 3. See Input Slew Rate Derating (page 53). 4. The slew rate for single-ended inputs is measured from DC level to AC level, V IL(DC) to V IH(AC) on the rising edge and V IL(AC) to V IH(DC) on the falling edge. For signals referenced to V REF, the valid intersection is where the “tangent” line intersects V REF, as shown in Figure 22 (page 56), Figure 24 (page 57), Figure 26 (page 62), and Figure 28 (page 63). 5. Input waveform hold ( t IH b) timing is referenced from the input signal crossing at the V IL(DC) level for a rising signal and V IH(DC) for a falling signal applied to the device under test, as shown in Figure 29 (page 64). 6. Input waveform setup timing ( t DS) and hold timing ( t DH) for single-ended data strobe is referenced from the crossing of DQS, UDQS, or LDQS through the Vref level applied to the device under test, as shown in Figure 31 (page 65). 7. Input waveform setup timing ( t DS) and hold timing ( t DH) when differential data strobe is enabled is referenced from the cross-point of DQS/DQS#, UDQS/UDQS#, or LDQS/ LDQS#, as shown in Figure 30 (page 64). 8. Input waveform timing is referenced to the crossing point level (V IX) of two input signals (V TR and V CP) applied to the device under test, where V TR is the true input signal and V CP is the complementary input signal, as shown in Figure 32 (page 65). 9. The slew rate for differentially ended inputs is measured from twice the DC level to twice the AC level: 2 × V IL(DC) to 2 × V IH(AC) on the rising edge and 2 × V IL(AC) to 2 × V IH(DC) on the falling edge. For example, the CK/CK# would be –250mV to 500mV for CK rising edge and would be 250mV to –500mV for CK falling edge. PDF: 09005aef840eff89 1gbddr2_ait_aat.pdf – Rev. C 7/11 EN 52 Micron Technology, Inc. reserves the right to change products or specifications without notice. � 2010 Micron Technology, Inc. All rights reserved.
Input Slew Rate Derating 1Gb: x8, x16 Automotive DDR2 SDRAM Input Slew Rate Derating For all input signals, the total t IS (setup time) and t IH (hold time) required is calculated by adding the data sheet t IS (base) and t IH (base) value to the Δ t IS and Δ t IH derating value, respectively. Example: t IS (total setup time) = t IS (base) + Δ t IS. tIS, the nominal slew rate for a rising signal, is defined as the slew rate between the last crossing of VREF(DC) and the first crossing of VIH(AC)min. Setup nominal slew rate ( tIS) for a falling signal is defined as the slew rate between the last crossing of VREF(DC) and the first crossing of VIL(AC)max. If the actual signal is always earlier than the nominal slew rate line between shaded “VREF(DC) to AC region,” use the nominal slew rate for the derating value (Figure 21 (page 56)). If the actual signal is later than the nominal slew rate line anywhere between the shaded “VREF(DC) to AC region,” the slew rate of a tangent line to the actual signal from the AC level to DC level is used for the derating value (see Figure 22 (page 56)). tIH, the nominal slew rate for a rising signal, is defined as the slew rate between the last crossing of VIL(DC)max and the first crossing of VREF(DC). tIH, nominal slew rate for a falling signal, is defined as the slew rate between the last crossing of VIH(DC)min and the first crossing of VREF(DC). If the actual signal is always later than the nominal slew rate line between shaded “DC to VREF(DC) region,” use the nominal slew rate for the derating value (Figure 23 (page 57)). If the actual signal is earlier than the nominal slew rate line anywhere between shaded “DC to VREF(DC) region,” the slew rate of a tangent line to the actual signal from the DC level to VREF(DC) level is used for the derating value (Figure 24 (page 57)). Although the total setup time might be negative for slow slew rates (a valid input signal will not have reached VIH[AC]/VIL[AC] at the time of the rising clock transition), a valid input signal is still required to complete the transition and reach VIH(AC)/VIL(AC). For slew rates in between the values listed in Table 28 (page 54) and Table 29 (page 55), the derating values may obtained by linear interpolation. PDF: 09005aef840eff89 1gbddr2_ait_aat.pdf – Rev. C 7/11 EN 53 Micron Technology, Inc. reserves the right to change products or specifications without notice. � 2010 Micron Technology, Inc. All rights reserved.
Page 1 and 2: Automotive DDR2 SDRAM MT47H128M8 -
Page 3 and 4: 1Gb: x8, x16 Automotive DDR2 SDRAM
Page 9 and 10: Functional Description Automotive I
Page 11 and 12: Functional Block Diagrams The DDR2
Page 13 and 14: Ball Assignments and Descriptions F
Page 15 and 16: Table 3: FBGA 84-Ball - x16 and 60-
Page 17 and 18: Packaging Package Dimensions Figure
Page 19 and 20: FBGA Package Capacitance Table 4: I
Page 21 and 22: Table 6: Temperature Limits Paramet
Page 23 and 24: I DD7 Conditions The detailed timin
Page 25 and 26: Table 10: DDR2 I DD Specifications
Page 27 and 28: PDF: 09005aef840eff89 Micron Techno
Page 39 and 40: AC and DC Operating Conditions Tabl
Page 41 and 42: Input Electrical Characteristics an
Page 45 and 46: Table 19: Output Characteristics Pa
Page 47 and 48: Figure 15: Full Strength Pull-Up Ch
Page 49 and 50: Figure 17: Reduced Strength Pull-Up
Page 51: AC Overshoot/Undershoot Specificati
Page 57 and 58: Figure 23: Nominal Slew Rate for t
Page 61 and 62: Table 34: Single-Ended DQS Slew Rat
Page 63 and 64: Figure 27: Nominal Slew Rate for t
Page 65 and 66: Figure 31: AC Input Test Signal Wav
Page 67 and 68: 6. Bank addresses (BA) determine wh
Page 69 and 70: Table 38: Truth Table - Current Sta
Page 71 and 72: NO OPERATION (NOP) LOAD MODE (LM) A
Page 73 and 74: Burst Length Figure 33: MR Definiti
Page 75 and 76: Write Recovery Power-Down Mode 1Gb:
Page 77 and 78: Extended Mode Register (EMR) Figure
Page 79 and 80: On-Die Termination (ODT) ODT effect
Page 81 and 82: Extended Mode Register 2 (EMR2) Fig
Page 87 and 88: Figure 42: Multibank Activate Restr
Page 89 and 90: Figure 43: READ Latency CK# CK Comm
Page 91 and 92: Figure 45: Nonconsecutive READ Burs
Page 93 and 94: Figure 48: READ-to-PRECHARGE - BL =
Page 95 and 96: Figure 50: Bank Read - Without Auto
Page 97 and 98: Figure 52: x4, x8 Data Output Timin
Page 99 and 100: Figure 54: Data Output Timing - t A
Page 101 and 102: Figure 55: Write Burst CK# CK Comma
Page 103 and 104:
Figure 58: WRITE Interrupted by WRI
Page 105 and 106:
Figure 60: WRITE-to-PRECHARGE CK# C
Page 107 and 108:
Figure 62: Bank Write - with Auto P
Page 109 and 110:
Figure 64: Data Input Timing PRECHA
Page 111 and 112:
SELF REFRESH 1Gb: x8, x16 Automotiv
Page 113 and 114:
Power-Down Mode 1Gb: x8, x16 Automo
Page 115 and 116:
Table 43: Truth Table - CKE 1Gb: x8
Page 117 and 118:
Figure 70: WRITE-to-Power-Down or S
Page 119 and 120:
Figure 74: PRECHARGE Command-to-Pow
Page 121 and 122:
Reset CKE Low Anytime 1Gb: x8, x16
Page 123 and 124:
ODT Timing 1Gb: x8, x16 Automotive
Page 125 and 126:
MRS Command to ODT Update Delay Dur
Page 127 and 128:
Figure 83: ODT Turn-On Timing When
Page 129:
Figure 85: ODT Turn-On Timing When
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1Gb: x8, x16 Automotive DDR2 SDRAM - Micron

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