1Gb: x8, x16 Automotive DDR2 SDRAM - Micron

Figure 48: READ-to-PRECHARGE – BL = 4
lowing the PRECHARGE command, a subsequent command to the same bank cannot
be issued until tRP is met. However, part of the row precharge time is hidden during the
access of the last data elements.
Examples of READ-to-PRECHARGE for BL = 4 are shown in Figure 48 and in Figure 49
for BL = 8. The delay from READ-to-PRECHARGE period to the same bank is AL + BL/2 -
2CK + MAX ( tRTP/ tCK or 2 × CK) where MAX means the larger of the two.
CK#
CK
T0
4-bit
prefetch
T1 T2
AL + BL/2 - 2CK + MAX (tRTP/tCK or 2CK)
T3 T4 T5 T6 T7
Command READ NOP NOP PRE NOP NOP ACT
NOP
Address Bank a Bank a Bank a
A10 Valid Valid
AL = 1
DQS, DQS#
�tRTP (MIN)
DQ DO DO DO DO
�tRAS (MIN)
CL = 3
�tRC (MIN)
�tRP (MIN)
Notes: 1. RL = 4 (AL = 1, CL = 3); BL = 4.
2. t RTP ≥ 2 clocks.
3. Shown with nominal t AC, t DQSCK, and t DQSQ.
Figure 49: READ-to-PRECHARGE – BL = 8
CK#
CK
DQS, DQS#
T0
First 4-bit
prefetch
T1 T2
AL = 1
CL = 3
Transitioning Data
Transitioning Data
Don’t Care
Second 4-bit
prefetch
T3 T4 T5 T6 T7 T8
Command READ NOP NOP NOP NOP PRE NOP NOP ACT
AL + BL/2 - 2CK + MAX (tRTP/tCK or 2CK)
Address Bank a Bank a Bank a
A10 Valid Valid
DQ DO DO DO DO DO DO DO DO
�tRAS (MIN)
�tRC (MIN)
�tRTP (MIN)
Notes: 1. RL = 4 (AL = 1, CL = 3); BL = 8.
2. t RTP ≥ 2 clocks.
3. Shown with nominal t AC, t DQSCK, and t DQSQ.
1Gb: x8, x16 Automotive DDR2 SDRAM
READ
�tRP (MIN)
Don’t Care
PDF: 09005aef840eff89
1gbddr2_ait_aat.pdf – Rev. C 7/11 EN 93 Micron Technology, Inc. reserves the right to change products or specifications without notice.
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