1Gb: x8, x16 Automotive DDR2 SDRAM - Micron

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Table 16: Differential Input Logic Levels All voltages referenced to VSS Parameter Symbol Min Max Units Notes DC input signal voltage VIN(DC) –300 VDDQ mV 1, 6 DC differential input voltage VID(DC) 250 VDDQ mV 2, 6 AC differential input voltage VID(AC) 500 VDDQ mV 3, 6 AC differential cross-point voltage VIX(AC) 0.50 × VDDQ - 175 0.50 × VDDQ + 175 mV 4 Input midpoint voltage VMP(DC) 850 950 mV 5 Notes: 1. V IN(DC) specifies the allowable DC execution of each input of differential pair such as CK, CK#, DQS, DQS#, LDQS, LDQS#, UDQS, UDQS#, and RDQS, RDQS#. 2. V ID(DC) specifies the input differential voltage |V TR - V CP| required for switching, where V TR is the true input (such as CK, DQS, LDQS, UDQS) level and V CP is the complementary input (such as CK#, DQS#, LDQS#, UDQS#) level. The minimum value is equal to V IH(DC) - V IL(DC). Differential input signal levels are shown in Figure 11. 3. V ID(AC) specifies the input differential voltage |V TR - V CP| required for switching, where V TR is the true input (such as CK, DQS, LDQS, UDQS, RDQS) level and V CP is the complementary input (such as CK#, DQS#, LDQS#, UDQS#, RDQS#) level. The minimum value is equal to V IH(AC) - V IL(AC), as shown in Table 15 (page 41). 4. The typical value of V IX(AC) is expected to be about 0.5 × V DDQ of the transmitting device and V IX(AC) is expected to track variations in V DDQ. V IX(AC) indicates the voltage at which differential input signals must cross, as shown in Figure 11. 5. V MP(DC) specifies the input differential common mode voltage (V TR + V CP)/2 where V TR is the true input (CK, DQS) level and V CP is the complementary input (CK#, DQS#). V MP(DC) is expected to be approximately 0.5 × V DDQ. 6. V DDQ + 300mV allowed provided 1.9V is not exceeded. Figure 11: Differential Input Signal Levels 2.1V V DDQ = 1.8V CP 2 1.075V 0.9V 0.725V TR 2 –0.30V 1Gb: x8, x16 Automotive DDR2 SDRAM Input Electrical Characteristics and Operating Conditions X X V IN(DC)max 1 V MP(DC) 3 V IX(AC) 4 Notes: 1. TR and CP may not be more positive than V DDQ + 0.3V or more negative than V SS - 0.3V. 2. TR represents the CK, DQS, RDQS, LDQS, and UDQS signals; CP represents CK#, DQS#, RDQS#, LDQS#, and UDQS# signals. 3. This provides a minimum of 850mV to a maximum of 950mV and is expected to be V DDQ/2. 4. TR and CP must cross in this region. 5. TR and CP must meet at least V ID(DC)min when static and is centered around V MP(DC). 6. TR and CP must have a minimum 500mV peak-to-peak swing. PDF: 09005aef840eff89 1gbddr2_ait_aat.pdf – Rev. C 7/11 EN 42 Micron Technology, Inc. reserves the right to change products or specifications without notice. � 2010 Micron Technology, Inc. All rights reserved. V IN(DC)min 1 V ID(DC) 5 V ID(AC) 6
1Gb: x8, x16 Automotive DDR2 SDRAM Input Electrical Characteristics and Operating Conditions 7. Numbers in diagram reflect nominal values (V DDQ = 1.8V). PDF: 09005aef840eff89 1gbddr2_ait_aat.pdf – Rev. C 7/11 EN 43 Micron Technology, Inc. reserves the right to change products or specifications without notice. � 2010 Micron Technology, Inc. All rights reserved.
Page 1 and 2: Automotive DDR2 SDRAM MT47H128M8 -
Page 3 and 4: 1Gb: x8, x16 Automotive DDR2 SDRAM
Page 9 and 10: Functional Description Automotive I
Page 11 and 12: Functional Block Diagrams The DDR2
Page 13 and 14: Ball Assignments and Descriptions F
Page 15 and 16: Table 3: FBGA 84-Ball - x16 and 60-
Page 17 and 18: Packaging Package Dimensions Figure
Page 19 and 20: FBGA Package Capacitance Table 4: I
Page 21 and 22: Table 6: Temperature Limits Paramet
Page 23 and 24: I DD7 Conditions The detailed timin
Page 25 and 26: Table 10: DDR2 I DD Specifications
Page 27 and 28: PDF: 09005aef840eff89 Micron Techno
Page 39 and 40: AC and DC Operating Conditions Tabl
Page 41: Input Electrical Characteristics an
Page 45 and 46: Table 19: Output Characteristics Pa
Page 47 and 48: Figure 15: Full Strength Pull-Up Ch
Page 49 and 50: Figure 17: Reduced Strength Pull-Up
Page 51 and 52: AC Overshoot/Undershoot Specificati
Page 53 and 54: Input Slew Rate Derating 1Gb: x8, x
Page 57 and 58: Figure 23: Nominal Slew Rate for t
Page 61 and 62: Table 34: Single-Ended DQS Slew Rat
Page 63 and 64: Figure 27: Nominal Slew Rate for t
Page 65 and 66: Figure 31: AC Input Test Signal Wav
Page 67 and 68: 6. Bank addresses (BA) determine wh
Page 69 and 70: Table 38: Truth Table - Current Sta
Page 71 and 72: NO OPERATION (NOP) LOAD MODE (LM) A
Page 73 and 74: Burst Length Figure 33: MR Definiti
Page 75 and 76: Write Recovery Power-Down Mode 1Gb:
Page 77 and 78: Extended Mode Register (EMR) Figure
Page 79 and 80: On-Die Termination (ODT) ODT effect
Page 81 and 82: Extended Mode Register 2 (EMR2) Fig
Page 87 and 88: Figure 42: Multibank Activate Restr
Page 89 and 90: Figure 43: READ Latency CK# CK Comm
Page 91 and 92: Figure 45: Nonconsecutive READ Burs
Page 93 and 94:
Figure 48: READ-to-PRECHARGE - BL =
Page 95 and 96:
Figure 50: Bank Read - Without Auto
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Figure 52: x4, x8 Data Output Timin
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Figure 54: Data Output Timing - t A
Page 101 and 102:
Figure 55: Write Burst CK# CK Comma
Page 103 and 104:
Figure 58: WRITE Interrupted by WRI
Page 105 and 106:
Figure 60: WRITE-to-PRECHARGE CK# C
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Figure 62: Bank Write - with Auto P
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Figure 64: Data Input Timing PRECHA
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SELF REFRESH 1Gb: x8, x16 Automotiv
Page 113 and 114:
Power-Down Mode 1Gb: x8, x16 Automo
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Table 43: Truth Table - CKE 1Gb: x8
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Figure 70: WRITE-to-Power-Down or S
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Figure 74: PRECHARGE Command-to-Pow
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Reset CKE Low Anytime 1Gb: x8, x16
Page 123 and 124:
ODT Timing 1Gb: x8, x16 Automotive
Page 125 and 126:
MRS Command to ODT Update Delay Dur
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Figure 83: ODT Turn-On Timing When
Page 129:
Figure 85: ODT Turn-On Timing When
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1Gb: x8, x16 Automotive DDR2 SDRAM - Micron

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