1Gb: x8, x16 Automotive DDR2 SDRAM - Micron
1Gb: x8, x16 Automotive DDR2 SDRAM - Micron
1Gb: x8, x16 Automotive DDR2 SDRAM - Micron
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Figure 70: WRITE-to-Power-Down or Self Refresh Entry<br />
CK#<br />
CK<br />
Command<br />
CKE<br />
Address<br />
A10<br />
DQS, DQS#<br />
DQ<br />
T0 T1 T2<br />
WRITE<br />
Valid<br />
NOP NOP<br />
NOP<br />
WL = 3<br />
T3 T4 T5<br />
DO<br />
Valid Valid<br />
DO DO DO<br />
T6<br />
Valid<br />
t WTR<br />
T7 T8<br />
NOP1<br />
Power-down or<br />
self refresh entry1<br />
Transitioning Data<br />
tCKE (MIN)<br />
Note: 1. Power-down or self refresh entry may occur after the WRITE burst completes.<br />
Figure 71: WRITE with Auto Precharge-to-Power-Down or Self Refresh Entry<br />
CK#<br />
CK<br />
Command<br />
CKE<br />
Address<br />
A10<br />
DQS, DQS#<br />
DQ<br />
T0 T1 T2<br />
WRITE<br />
Valid<br />
NOP NOP<br />
NOP<br />
WL = 3<br />
T3 T4 T5<br />
DO<br />
Valid Valid<br />
DO DO DO<br />
<strong>1Gb</strong>: <strong>x8</strong>, <strong>x16</strong> <strong>Automotive</strong> <strong>DDR2</strong> <strong>SDRAM</strong><br />
Power-Down Mode<br />
WR2<br />
Indicates a break in<br />
time scale<br />
Ta0<br />
Valid1 NOP<br />
Transitioning Data<br />
Ta1 Ta2<br />
Power-down or<br />
self refresh entry<br />
t CKE (MIN)<br />
Don’t Care<br />
Don’t Care<br />
Notes: 1. Internal PRECHARGE occurs at Ta0 when WR has completed; power-down entry may occur<br />
1 x t CK later at Ta1, prior to t RP being satisfied.<br />
2. WR is programmed through MR9–MR11 and represents ( t WR [MIN] ns/ t CK) rounded up<br />
to next integer t CK.<br />
PDF: 09005aef840eff89<br />
1gbddr2_ait_aat.pdf – Rev. C 7/11 EN 117 <strong>Micron</strong> Technology, Inc. reserves the right to change products or specifications without notice.<br />
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