1Gb: x8, x16 Automotive DDR2 SDRAM - Micron

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Figure 81: ODT Timing for Slow-Exit or Precharge Power-Down Modes CK# CK Command Address CKE ODT R TT T0 T1 T2 T3 T4 T5 T6 t CH t CL Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid t AONPD (MIN) t AONPD (MAX) t AOFPD (MIN) Transitioning R TT Figure 82: ODT Turn-Off Timings When Entering Power-Down Mode CK# CK Command CKE ODT R TT ODT R TT t CK 1Gb: x8, x16 Automotive DDR2 SDRAM ODT Timing t AOFPD (MAX) R TT Unknown R TT On T0 T1 T2 T3 T4 T5 T6 NOP NOP NOP NOP NOP NOP NOP t ANPD (MIN) t AOFD t AOF (MIN) t AOFPD (MAX) t AOFPD (MIN) Transitioning R TT R TT Unknown R TT ON t AOF (MAX) T7 Valid Valid Don’t Care Don’t Care PDF: 09005aef840eff89 1gbddr2_ait_aat.pdf – Rev. C 7/11 EN 126 Micron Technology, Inc. reserves the right to change products or specifications without notice. � 2010 Micron Technology, Inc. All rights reserved.
Figure 83: ODT Turn-On Timing When Entering Power-Down Mode CK# CK Command CKE ODT R TT ODT R TT 1Gb: x8, x16 Automotive DDR2 SDRAM ODT Timing T0 T1 T2 T3 T4 T5 T6 NOP NOP NOP NOP NOP NOP NOP t AOND t ANPD (MIN) t AON (MIN) t AONPD (MAX) t AONPD (MIN) t AON (MAX) Transitioning R TT R TT Unknown R TT On Don’t Care PDF: 09005aef840eff89 1gbddr2_ait_aat.pdf – Rev. C 7/11 EN 127 Micron Technology, Inc. reserves the right to change products or specifications without notice. � 2010 Micron Technology, Inc. All rights reserved.
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Automotive DDR2 SDRAM MT47H128M8 -
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1Gb: x8, x16 Automotive DDR2 SDRAM
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Functional Description Automotive I
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Functional Block Diagrams The DDR2
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Ball Assignments and Descriptions F
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Table 3: FBGA 84-Ball - x16 and 60-
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Packaging Package Dimensions Figure
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FBGA Package Capacitance Table 4: I
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Table 6: Temperature Limits Paramet
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I DD7 Conditions The detailed timin
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Table 10: DDR2 I DD Specifications
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PDF: 09005aef840eff89 Micron Techno
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AC and DC Operating Conditions Tabl
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Input Electrical Characteristics an
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Table 19: Output Characteristics Pa
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Figure 15: Full Strength Pull-Up Ch
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Figure 17: Reduced Strength Pull-Up
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AC Overshoot/Undershoot Specificati
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Input Slew Rate Derating 1Gb: x8, x
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Figure 23: Nominal Slew Rate for t
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Table 34: Single-Ended DQS Slew Rat
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Figure 27: Nominal Slew Rate for t
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Figure 31: AC Input Test Signal Wav
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6. Bank addresses (BA) determine wh
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Table 38: Truth Table - Current Sta
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NO OPERATION (NOP) LOAD MODE (LM) A
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Burst Length Figure 33: MR Definiti
Page 75 and 76: Write Recovery Power-Down Mode 1Gb:
Page 77 and 78: Extended Mode Register (EMR) Figure
Page 79 and 80: On-Die Termination (ODT) ODT effect
Page 81 and 82: Extended Mode Register 2 (EMR2) Fig
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Page 85 and 86: 1Gb: x8, x16 Automotive DDR2 SDRAM
Page 87 and 88: Figure 42: Multibank Activate Restr
Page 89 and 90: Figure 43: READ Latency CK# CK Comm
Page 91 and 92: Figure 45: Nonconsecutive READ Burs
Page 93 and 94: Figure 48: READ-to-PRECHARGE - BL =
Page 95 and 96: Figure 50: Bank Read - Without Auto
Page 97 and 98: Figure 52: x4, x8 Data Output Timin
Page 99 and 100: Figure 54: Data Output Timing - t A
Page 101 and 102: Figure 55: Write Burst CK# CK Comma
Page 103 and 104: Figure 58: WRITE Interrupted by WRI
Page 105 and 106: Figure 60: WRITE-to-PRECHARGE CK# C
Page 107 and 108: Figure 62: Bank Write - with Auto P
Page 109 and 110: Figure 64: Data Input Timing PRECHA
Page 111 and 112: SELF REFRESH 1Gb: x8, x16 Automotiv
Page 113 and 114: Power-Down Mode 1Gb: x8, x16 Automo
Page 115 and 116: Table 43: Truth Table - CKE 1Gb: x8
Page 117 and 118: Figure 70: WRITE-to-Power-Down or S
Page 119 and 120: Figure 74: PRECHARGE Command-to-Pow
Page 121 and 122: Reset CKE Low Anytime 1Gb: x8, x16
Page 123 and 124: ODT Timing 1Gb: x8, x16 Automotive
Page 125: MRS Command to ODT Update Delay Dur
Page 129: Figure 85: ODT Turn-On Timing When
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1Gb: x8, x16 Automotive DDR2 SDRAM - Micron

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