1Gb: x8, x16 Automotive DDR2 SDRAM - Micron

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Figure 44: Consecutive READ Bursts CK# CK Command READ NOP READ NOP NOP NOP NOP Address DQS, DQS# DQ CK# CK Bank, Col n Bank, Col b Command READ NOP READ NOP NOP NOP Address DQS, DQS# DQ T0 T1 T2 T3 T3n T4 T4n T5 T5n T6 T6n Bank, Col n t CCD RL = 3 T0 T1 T2 T2n T3 t CCD RL = 4 Bank, Col b 1Gb: x8, x16 Automotive DDR2 SDRAM READ DO n T3n T4 T4n T5 T5n T6 T6n DO n DO b Transitioning Data NOP DO b Don’t Care Notes: 1. DO n (or b) = data-out from column n (or column b). 2. BL = 4. 3. Three subsequent elements of data-out appear in the programmed order following DO n. 4. Three subsequent elements of data-out appear in the programmed order following DO b. 5. Shown with nominal t AC, t DQSCK, and t DQSQ. 6. Example applies only when READ commands are issued to same device. PDF: 09005aef840eff89 1gbddr2_ait_aat.pdf – Rev. C 7/11 EN 90 Micron Technology, Inc. reserves the right to change products or specifications without notice. � 2010 Micron Technology, Inc. All rights reserved.
Figure 45: Nonconsecutive READ Bursts CK# CK T0 T1 T2 T3 T3n T4 T4n T5 T6 T6n T7 T7n T8 Command READ NOP NOP READ NOP NOP NOP NOP NOP Address DQS, DQS# DQ CK# CK T0 T1 T2 T3 T4 DO n T4n T5 T5n T6 T7 T7n T8 Command READ NOP NOP READ NOP NOP NOP NOP NOP Address DQS, DQS# DQ Bank, Col n Bank, Col n CL = 3 CL = 4 1Gb: x8, x16 Automotive DDR2 SDRAM READ Bank, Col b Bank, Col b DO n DO b Transitioning Data DO b Don’t Care Notes: 1. DO n (or b) = data-out from column n (or column b). 2. BL = 4. 3. Three subsequent elements of data-out appear in the programmed order following DO n. 4. Three subsequent elements of data-out appear in the programmed order following DO b. 5. Shown with nominal t AC, t DQSCK, and t DQSQ. 6. Example applies when READ commands are issued to different devices or nonconsecutive READs. PDF: 09005aef840eff89 1gbddr2_ait_aat.pdf – Rev. C 7/11 EN 91 Micron Technology, Inc. reserves the right to change products or specifications without notice. � 2010 Micron Technology, Inc. All rights reserved.
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Automotive DDR2 SDRAM MT47H128M8 -
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1Gb: x8, x16 Automotive DDR2 SDRAM
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Functional Description Automotive I
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Functional Block Diagrams The DDR2
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Ball Assignments and Descriptions F
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Table 3: FBGA 84-Ball - x16 and 60-
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Packaging Package Dimensions Figure
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FBGA Package Capacitance Table 4: I
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Table 6: Temperature Limits Paramet
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I DD7 Conditions The detailed timin
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Table 10: DDR2 I DD Specifications
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PDF: 09005aef840eff89 Micron Techno
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Page 39 and 40: AC and DC Operating Conditions Tabl
Page 41 and 42: Input Electrical Characteristics an
Page 43 and 44: 1Gb: x8, x16 Automotive DDR2 SDRAM
Page 45 and 46: Table 19: Output Characteristics Pa
Page 47 and 48: Figure 15: Full Strength Pull-Up Ch
Page 49 and 50: Figure 17: Reduced Strength Pull-Up
Page 51 and 52: AC Overshoot/Undershoot Specificati
Page 53 and 54: Input Slew Rate Derating 1Gb: x8, x
Page 57 and 58: Figure 23: Nominal Slew Rate for t
Page 61 and 62: Table 34: Single-Ended DQS Slew Rat
Page 63 and 64: Figure 27: Nominal Slew Rate for t
Page 65 and 66: Figure 31: AC Input Test Signal Wav
Page 67 and 68: 6. Bank addresses (BA) determine wh
Page 69 and 70: Table 38: Truth Table - Current Sta
Page 71 and 72: NO OPERATION (NOP) LOAD MODE (LM) A
Page 73 and 74: Burst Length Figure 33: MR Definiti
Page 75 and 76: Write Recovery Power-Down Mode 1Gb:
Page 77 and 78: Extended Mode Register (EMR) Figure
Page 79 and 80: On-Die Termination (ODT) ODT effect
Page 81 and 82: Extended Mode Register 2 (EMR2) Fig
Page 83 and 84: PDF: 09005aef840eff89 Micron Techno
Page 87 and 88: Figure 42: Multibank Activate Restr
Page 89: Figure 43: READ Latency CK# CK Comm
Page 93 and 94: Figure 48: READ-to-PRECHARGE - BL =
Page 95 and 96: Figure 50: Bank Read - Without Auto
Page 97 and 98: Figure 52: x4, x8 Data Output Timin
Page 99 and 100: Figure 54: Data Output Timing - t A
Page 101 and 102: Figure 55: Write Burst CK# CK Comma
Page 103 and 104: Figure 58: WRITE Interrupted by WRI
Page 105 and 106: Figure 60: WRITE-to-PRECHARGE CK# C
Page 107 and 108: Figure 62: Bank Write - with Auto P
Page 109 and 110: Figure 64: Data Input Timing PRECHA
Page 111 and 112: SELF REFRESH 1Gb: x8, x16 Automotiv
Page 113 and 114: Power-Down Mode 1Gb: x8, x16 Automo
Page 115 and 116: Table 43: Truth Table - CKE 1Gb: x8
Page 117 and 118: Figure 70: WRITE-to-Power-Down or S
Page 119 and 120: Figure 74: PRECHARGE Command-to-Pow
Page 121 and 122: Reset CKE Low Anytime 1Gb: x8, x16
Page 123 and 124: ODT Timing 1Gb: x8, x16 Automotive
Page 125 and 126: MRS Command to ODT Update Delay Dur
Page 127 and 128: Figure 83: ODT Turn-On Timing When
Page 129: Figure 85: ODT Turn-On Timing When
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1Gb: x8, x16 Automotive DDR2 SDRAM - Micron

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