1Gb: x8, x16 Automotive DDR2 SDRAM - Micron

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Figure 77: RESET Function CK# CK CKE ODT Command NOP2 READ NOP PRE 2 READ NOP2 NOP2 DM3 Address A10 Bank address DQS3 DQ3 R TT T0 T1 T2 Col n Bank a High-Z High-Z Col n Bank b T3 T4 T5 DO DO DO Indicates a break in time scale System RESET 1Gb: x8, x16 Automotive DDR2 SDRAM Reset tDELAY Unknown R TT On 1 High-Z High-Z tCL tCK tCL Ta0 � Transitioning Data tCKE (MIN) T = 400ns (MIN) Start of normal 5 initialization sequence Tb0 All banks High-Z tRPA Don’t Care Notes: 1. V DD, V DDL, V DDQ, V TT, and V REF must be valid at all times. 2. Either NOP or DESELECT command may be applied. 3. DM represents DM for x4/x8 configuration and UDM, LDM for x16 configuration. DQS represents DQS, DQS#, UDQS, UDQS#, LDQS, LDQS#, RDQS, and RDQS# for the appropriate configuration (x4, x8, x16). 4. In certain cases where a READ cycle is interrupted, CKE going HIGH may result in the completion of the burst. 5. Initialization timing is shown in Figure 40 (page 83). PDF: 09005aef840eff89 1gbddr2_ait_aat.pdf – Rev. C 7/11 EN 122 Micron Technology, Inc. reserves the right to change products or specifications without notice. � 2010 Micron Technology, Inc. All rights reserved.
ODT Timing 1Gb: x8, x16 Automotive DDR2 SDRAM ODT Timing Once a 12ns delay ( tMOD) has been satisfied, and after the ODT function has been enabled via the EMR LOAD MODE command, ODT can be accessed under two timing categories. ODT will operate either in synchronous mode or asynchronous mode, depending on the state of CKE. ODT can switch anytime except during self refresh mode and a few clocks after being enabled via EMR, as shown in Figure 78 (page 124). There are two timing categories for ODT—turn-on and turn-off. During active mode (CKE HIGH) and fast-exit power-down mode (any row of any bank open, CKE LOW, MR[12 = 0]), tAOND, tAON, tAOFD, and tAOF timing parameters are applied, as shown in Figure 80 (page 125). During slow-exit power-down mode (any row of any bank open, CKE LOW, MR[12] = 1) and precharge power-down mode (all banks/rows precharged and idle, CKE LOW), tAONPD and tAOFPD timing parameters are applied, as shown in Figure 81 (page 126). ODT turn-off timing, prior to entering any power-down mode, is determined by the parameter tANPD (MIN), as shown in Figure 82 (page 126). At state T2, the ODT HIGH signal satisfies tANPD (MIN) prior to entering power-down mode at T5. When tANPD (MIN) is satisfied, tAOFD and tAOF timing parameters apply. Figure 82 (page 126) also shows the example where tANPD (MIN) is not satisfied because ODT HIGH does not occur until state T3. When tANPD (MIN) is not satisfied, tAOFPD timing parameters apply. ODT turn-on timing prior to entering any power-down mode is determined by the parameter tANPD, as shown in Figure 83 (page 127). At state T2, the ODT HIGH signal satisfies tANPD (MIN) prior to entering power-down mode at T5. When tANPD (MIN) is satisfied, tAOND and tAON timing parameters apply. Figure 83 (page 127) also shows the example where tANPD (MIN) is not satisfied because ODT HIGH does not occur until state T3. When tANPD (MIN) is not satisfied, tAONPD timing parameters apply. ODT turn-off timing after exiting any power-down mode is determined by the parameter tAXPD (MIN), as shown in Figure 84 (page 128). At state Ta1, the ODT LOW signal satisfies tAXPD (MIN) after exiting power-down mode at state T1. When tAXPD (MIN) is satisfied, tAOFD and tAOF timing parameters apply. Figure 84 (page 128) also shows the example where tAXPD (MIN) is not satisfied because ODT LOW occurs at state Ta0. When tAXPD (MIN) is not satisfied, tAOFPD timing parameters apply. ODT turn-on timing after exiting either slow-exit power-down mode or precharge power-down mode is determined by the parameter tAXPD (MIN), as shown in Figure 85 (page 129). At state Ta1, the ODT HIGH signal satisfies tAXPD (MIN) after exiting power-down mode at state T1. When tAXPD (MIN) is satisfied, tAOND and tAON timing parameters apply. Figure 85 (page 129) also shows the example where tAXPD (MIN) is not satisfied because ODT HIGH occurs at state Ta0. When tAXPD (MIN) is not satisfied, tAONPD timing parameters apply. PDF: 09005aef840eff89 1gbddr2_ait_aat.pdf – Rev. C 7/11 EN 123 Micron Technology, Inc. reserves the right to change products or specifications without notice. � 2010 Micron Technology, Inc. All rights reserved.
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Automotive DDR2 SDRAM MT47H128M8 -
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1Gb: x8, x16 Automotive DDR2 SDRAM
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Functional Description Automotive I
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Functional Block Diagrams The DDR2
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Ball Assignments and Descriptions F
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Table 3: FBGA 84-Ball - x16 and 60-
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Packaging Package Dimensions Figure
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FBGA Package Capacitance Table 4: I
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Table 6: Temperature Limits Paramet
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I DD7 Conditions The detailed timin
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Table 10: DDR2 I DD Specifications
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PDF: 09005aef840eff89 Micron Techno
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AC and DC Operating Conditions Tabl
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Input Electrical Characteristics an
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Table 19: Output Characteristics Pa
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Figure 15: Full Strength Pull-Up Ch
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Figure 17: Reduced Strength Pull-Up
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AC Overshoot/Undershoot Specificati
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Input Slew Rate Derating 1Gb: x8, x
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Figure 23: Nominal Slew Rate for t
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Table 34: Single-Ended DQS Slew Rat
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Figure 27: Nominal Slew Rate for t
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Figure 31: AC Input Test Signal Wav
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6. Bank addresses (BA) determine wh
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Table 38: Truth Table - Current Sta
Page 71 and 72: NO OPERATION (NOP) LOAD MODE (LM) A
Page 73 and 74: Burst Length Figure 33: MR Definiti
Page 75 and 76: Write Recovery Power-Down Mode 1Gb:
Page 77 and 78: Extended Mode Register (EMR) Figure
Page 79 and 80: On-Die Termination (ODT) ODT effect
Page 81 and 82: Extended Mode Register 2 (EMR2) Fig
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Page 85 and 86: 1Gb: x8, x16 Automotive DDR2 SDRAM
Page 87 and 88: Figure 42: Multibank Activate Restr
Page 89 and 90: Figure 43: READ Latency CK# CK Comm
Page 91 and 92: Figure 45: Nonconsecutive READ Burs
Page 93 and 94: Figure 48: READ-to-PRECHARGE - BL =
Page 95 and 96: Figure 50: Bank Read - Without Auto
Page 97 and 98: Figure 52: x4, x8 Data Output Timin
Page 99 and 100: Figure 54: Data Output Timing - t A
Page 101 and 102: Figure 55: Write Burst CK# CK Comma
Page 103 and 104: Figure 58: WRITE Interrupted by WRI
Page 105 and 106: Figure 60: WRITE-to-PRECHARGE CK# C
Page 107 and 108: Figure 62: Bank Write - with Auto P
Page 109 and 110: Figure 64: Data Input Timing PRECHA
Page 111 and 112: SELF REFRESH 1Gb: x8, x16 Automotiv
Page 113 and 114: Power-Down Mode 1Gb: x8, x16 Automo
Page 115 and 116: Table 43: Truth Table - CKE 1Gb: x8
Page 117 and 118: Figure 70: WRITE-to-Power-Down or S
Page 119 and 120: Figure 74: PRECHARGE Command-to-Pow
Page 121: Reset CKE Low Anytime 1Gb: x8, x16
Page 125 and 126: MRS Command to ODT Update Delay Dur
Page 127 and 128: Figure 83: ODT Turn-On Timing When
Page 129: Figure 85: ODT Turn-On Timing When
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1Gb: x8, x16 Automotive DDR2 SDRAM - Micron

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