1Gb: x8, x16 Automotive DDR2 SDRAM - Micron

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ODT DC Electrical Characteristics Table 13: ODT DC Electrical Characteristics 1Gb: x8, x16 Automotive DDR2 SDRAM ODT DC Electrical Characteristics All voltages are referenced to VSS Parameter Symbol Min Nom Max Units Notes RTT effective impedance value for 75Ω setting EMR (A6, A2) = 0, 1 RTT1(EFF) 60 75 90 Ω 1, 2 RTT effective impedance value for 150Ω setting EMR (A6, A2) = 1, 0 RTT2(EFF) 120 150 180 Ω 1, 2 RTT effective impedance value for 50Ω setting EMR (A6, A2) = 1, 1 RTT3(EFF) 40 50 60 Ω 1, 2 Deviation of VM with respect to VDDQ/2 ΔVM –6 – 6 % 3 Notes: 1. R TT1(EFF) and R TT2(EFF) are determined by separately applying V IH(AC) and V IL(DC) to the ball being tested, and then measuring current, I(V IH[AC]), and I(V IL[AC]), respectively. 2. Minimum IT and AT device values are derated by six percent less when the devices operate between –40°C and 0°C (T C ). 3. Measure voltage (VM) at tested ball with no load. PDF: 09005aef840eff89 1gbddr2_ait_aat.pdf – Rev. C 7/11 EN 40 Micron Technology, Inc. reserves the right to change products or specifications without notice. � 2010 Micron Technology, Inc. All rights reserved.
Input Electrical Characteristics and Operating Conditions Table 14: Input DC Logic Levels All voltages are referenced to VSS Parameter Symbol Min Max Units Input high (logic 1) voltage VIH(DC) VREF(DC) + 125 V 1 DDQ mV Input low (logic 0) voltage VIL(DC) –300 VREF(DC) - 125 mV Table 15: Input AC Logic Levels Note: 1. V DDQ + 300mV allowed provided 1.9V is not exceeded. All voltages are referenced to VSS Parameter Symbol Min Max Units Input high (logic 1) voltage (-37E/-5E) VIH(AC) VREF(DC) + 250 V 1 DDQ mV Input high (logic 1) voltage (-187E/-25E/-25/-3E/-3) VIH(AC) VREF(DC) + 200 V 1 DDQ mV Input low (logic 0) voltage (-37E/-5E) VIL(AC) –300 VREF(DC) - 250 mV Input low (logic 0) voltage (-187E/-25E/-25/-3E/-3) VIL(AC) –300 VREF(DC) - 200 mV Note: 1. Refer to AC Overshoot/Undershoot Specification (page 51). Figure 10: Single-Ended Input Signal Levels 1,150mV 1,025mV 936mV 918mV 900mV 882mV 864mV 775mV 650mV 1Gb: x8, x16 Automotive DDR2 SDRAM Input Electrical Characteristics and Operating Conditions V IH(AC) V IH(DC) VREF + AC noise VREF + DC error VREF - DC error VREF - AC noise Note: 1. Numbers in diagram reflect nominal DDR2-400/DDR2-533 values. PDF: 09005aef840eff89 1gbddr2_ait_aat.pdf – Rev. C 7/11 EN 41 Micron Technology, Inc. reserves the right to change products or specifications without notice. � 2010 Micron Technology, Inc. All rights reserved. V IL(DC) V IL(AC)
Page 1 and 2: Automotive DDR2 SDRAM MT47H128M8 -
Page 3 and 4: 1Gb: x8, x16 Automotive DDR2 SDRAM
Page 9 and 10: Functional Description Automotive I
Page 11 and 12: Functional Block Diagrams The DDR2
Page 13 and 14: Ball Assignments and Descriptions F
Page 15 and 16: Table 3: FBGA 84-Ball - x16 and 60-
Page 17 and 18: Packaging Package Dimensions Figure
Page 19 and 20: FBGA Package Capacitance Table 4: I
Page 21 and 22: Table 6: Temperature Limits Paramet
Page 23 and 24: I DD7 Conditions The detailed timin
Page 25 and 26: Table 10: DDR2 I DD Specifications
Page 27 and 28: PDF: 09005aef840eff89 Micron Techno
Page 39: AC and DC Operating Conditions Tabl
Page 45 and 46: Table 19: Output Characteristics Pa
Page 47 and 48: Figure 15: Full Strength Pull-Up Ch
Page 49 and 50: Figure 17: Reduced Strength Pull-Up
Page 51 and 52: AC Overshoot/Undershoot Specificati
Page 53 and 54: Input Slew Rate Derating 1Gb: x8, x
Page 57 and 58: Figure 23: Nominal Slew Rate for t
Page 61 and 62: Table 34: Single-Ended DQS Slew Rat
Page 63 and 64: Figure 27: Nominal Slew Rate for t
Page 65 and 66: Figure 31: AC Input Test Signal Wav
Page 67 and 68: 6. Bank addresses (BA) determine wh
Page 69 and 70: Table 38: Truth Table - Current Sta
Page 71 and 72: NO OPERATION (NOP) LOAD MODE (LM) A
Page 73 and 74: Burst Length Figure 33: MR Definiti
Page 75 and 76: Write Recovery Power-Down Mode 1Gb:
Page 77 and 78: Extended Mode Register (EMR) Figure
Page 79 and 80: On-Die Termination (ODT) ODT effect
Page 81 and 82: Extended Mode Register 2 (EMR2) Fig
Page 87 and 88: Figure 42: Multibank Activate Restr
Page 89 and 90: Figure 43: READ Latency CK# CK Comm
Page 91 and 92:
Figure 45: Nonconsecutive READ Burs
Page 93 and 94:
Figure 48: READ-to-PRECHARGE - BL =
Page 95 and 96:
Figure 50: Bank Read - Without Auto
Page 97 and 98:
Figure 52: x4, x8 Data Output Timin
Page 99 and 100:
Figure 54: Data Output Timing - t A
Page 101 and 102:
Figure 55: Write Burst CK# CK Comma
Page 103 and 104:
Figure 58: WRITE Interrupted by WRI
Page 105 and 106:
Figure 60: WRITE-to-PRECHARGE CK# C
Page 107 and 108:
Figure 62: Bank Write - with Auto P
Page 109 and 110:
Figure 64: Data Input Timing PRECHA
Page 111 and 112:
SELF REFRESH 1Gb: x8, x16 Automotiv
Page 113 and 114:
Power-Down Mode 1Gb: x8, x16 Automo
Page 115 and 116:
Table 43: Truth Table - CKE 1Gb: x8
Page 117 and 118:
Figure 70: WRITE-to-Power-Down or S
Page 119 and 120:
Figure 74: PRECHARGE Command-to-Pow
Page 121 and 122:
Reset CKE Low Anytime 1Gb: x8, x16
Page 123 and 124:
ODT Timing 1Gb: x8, x16 Automotive
Page 125 and 126:
MRS Command to ODT Update Delay Dur
Page 127 and 128:
Figure 83: ODT Turn-On Timing When
Page 129:
Figure 85: ODT Turn-On Timing When
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1Gb: x8, x16 Automotive DDR2 SDRAM - Micron

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