1Gb: x8, x16 Automotive DDR2 SDRAM - Micron

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PDF: 09005aef840eff89 Micron Technology, Inc. reserves the right to change products or specifications without notice. 1gbddr2_ait_aat.pdf – Rev. C 7/11 EN 38 � 2010 Micron Technology, Inc. All rights reserved. 45. The half-clock of t AOFD’s 2.5 t CK assumes a 50/50 clock duty cycle. This half-clock value must be derated by the amount of half-clock duty cycle error. For example, if the clock duty cycle was 47/53, t AOFD would actually be 2.5 - 0.03, or 2.47, for t AOF (MIN) and 2.5 + 0.03, or 2.53, for t AOF (MAX). 46. ODT turn-on time t AON (MIN) is when the device leaves High-Z and ODT resistance begins to turn on. ODT turnon time t AON (MAX) is when the ODT resistance is fully on. Both are measured from t AOND. 47. ODT turn-off time t AOF (MIN) is when the device starts to turn off ODT resistance. ODT turn off time t AOF (MAX) is when the bus is in High-Z. Both are measured from t AOFD. 48. Half-clock output parameters must be derated by the actual t ERR 5per and t JITdty when input clock jitter is present; this will result in each parameter becoming larger. The parameter t AOF (MIN) is required to be derated by subtracting both t ERR 5per (MAX) and t JITdty (MAX). The parameter t AOF (MAX) is required to be derated by subtracting both t ERR 5per (MIN) and t JITdty (MIN). 49. The -187E maximum limit is 2 × t CK + t AC (MAX) + 1000 but it will likely be 3 x t CK + t AC (MAX) + 1000 in the future. 50. Should use 8 t CK for backward compatibility. 51. DRAM devices should be evenly addressed when being accessed. Disproportionate accesses to a particular row address may result in reduction of the product lifetime. 1Gb: x8, x16 Automotive DDR2 SDRAM AC Timing Operating Specifications
AC and DC Operating Conditions Table 12: Recommended DC Operating Conditions (SSTL_18) 1Gb: x8, x16 Automotive DDR2 SDRAM AC and DC Operating Conditions All voltages referenced to VSS Parameter Symbol Min Nom Max Units Notes Supply voltage VDD 1.7 1.8 1.9 V 1, 2 VDDL supply voltage VDDL 1.7 1.8 1.9 V 2, 3 I/O supply voltage VDDQ 1.7 1.8 1.9 V 2, 3 I/O reference voltage VREF(DC) 0.49 × VDDQ 0.50 × VDDQ 0.51 × VDDQ V 4 I/O termination voltage (system) VTT VREF(DC) - 40 VREF(DC) VREF(DC) + 40 mV 5 Notes: 1. V DD and V DDQ must track each other. V DDQ must be ≤ V DD. 2. V SSQ = V SSL = V SS. 3. V DDQ tracks with V DD; V DDL tracks with V DD. 4. V REF is expected to equal V DDQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise (noncommon mode) on V REF may not exceed ±1 percent of the DC value. Peak-to-peak AC noise on V REF may not exceed ±2 percent of V REF(DC). This measurement is to be taken at the nearest V REF bypass capacitor. 5. V TT is not applied directly to the device. V TT is a system supply for signal termination resistors, is expected to be set equal to V REF, and must track variations in the DC level of V REF. PDF: 09005aef840eff89 1gbddr2_ait_aat.pdf – Rev. C 7/11 EN 39 Micron Technology, Inc. reserves the right to change products or specifications without notice. � 2010 Micron Technology, Inc. All rights reserved.
Page 1 and 2: Automotive DDR2 SDRAM MT47H128M8 -
Page 3 and 4: 1Gb: x8, x16 Automotive DDR2 SDRAM
Page 9 and 10: Functional Description Automotive I
Page 11 and 12: Functional Block Diagrams The DDR2
Page 13 and 14: Ball Assignments and Descriptions F
Page 15 and 16: Table 3: FBGA 84-Ball - x16 and 60-
Page 17 and 18: Packaging Package Dimensions Figure
Page 19 and 20: FBGA Package Capacitance Table 4: I
Page 21 and 22: Table 6: Temperature Limits Paramet
Page 23 and 24: I DD7 Conditions The detailed timin
Page 25 and 26: Table 10: DDR2 I DD Specifications
Page 27 and 28: PDF: 09005aef840eff89 Micron Techno
Page 37: PDF: 09005aef840eff89 Micron Techno
Page 41 and 42: Input Electrical Characteristics an
Page 45 and 46: Table 19: Output Characteristics Pa
Page 47 and 48: Figure 15: Full Strength Pull-Up Ch
Page 49 and 50: Figure 17: Reduced Strength Pull-Up
Page 51 and 52: AC Overshoot/Undershoot Specificati
Page 53 and 54: Input Slew Rate Derating 1Gb: x8, x
Page 57 and 58: Figure 23: Nominal Slew Rate for t
Page 61 and 62: Table 34: Single-Ended DQS Slew Rat
Page 63 and 64: Figure 27: Nominal Slew Rate for t
Page 65 and 66: Figure 31: AC Input Test Signal Wav
Page 67 and 68: 6. Bank addresses (BA) determine wh
Page 69 and 70: Table 38: Truth Table - Current Sta
Page 71 and 72: NO OPERATION (NOP) LOAD MODE (LM) A
Page 73 and 74: Burst Length Figure 33: MR Definiti
Page 75 and 76: Write Recovery Power-Down Mode 1Gb:
Page 77 and 78: Extended Mode Register (EMR) Figure
Page 79 and 80: On-Die Termination (ODT) ODT effect
Page 81 and 82: Extended Mode Register 2 (EMR2) Fig
Page 87 and 88: Figure 42: Multibank Activate Restr
Page 89 and 90:
Figure 43: READ Latency CK# CK Comm
Page 91 and 92:
Figure 45: Nonconsecutive READ Burs
Page 93 and 94:
Figure 48: READ-to-PRECHARGE - BL =
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Figure 50: Bank Read - Without Auto
Page 97 and 98:
Figure 52: x4, x8 Data Output Timin
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Figure 54: Data Output Timing - t A
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Figure 55: Write Burst CK# CK Comma
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Figure 58: WRITE Interrupted by WRI
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Figure 60: WRITE-to-PRECHARGE CK# C
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Figure 62: Bank Write - with Auto P
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Figure 64: Data Input Timing PRECHA
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SELF REFRESH 1Gb: x8, x16 Automotiv
Page 113 and 114:
Power-Down Mode 1Gb: x8, x16 Automo
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Table 43: Truth Table - CKE 1Gb: x8
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Figure 70: WRITE-to-Power-Down or S
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Figure 74: PRECHARGE Command-to-Pow
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Reset CKE Low Anytime 1Gb: x8, x16
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ODT Timing 1Gb: x8, x16 Automotive
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MRS Command to ODT Update Delay Dur
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Figure 83: ODT Turn-On Timing When
Page 129:
Figure 85: ODT Turn-On Timing When
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1Gb: x8, x16 Automotive DDR2 SDRAM - Micron

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