1Gb: x8, x16 Automotive DDR2 SDRAM - Micron

Table 10: DDR2 I DD Specifications and Conditions (Die Revision H) (Continued)
Notes: 1–7 apply to the entire table
-25E/ -3E/
Parameter/Condition Symbol Configuration -25 -3 Units
Operating burst read current: All banks open,
continuous burst reads, IOUT = 0mA; BL = 4, CL = CL
(IDD), AL = 0; tCK = tCK (IDD), tRAS = t IDD4R x8 120 110 mA
RAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, CS# is HIGH between
valid commands; Address bus inputs are switching;
Data bus inputs are switching
x16 150 125
Burst refresh current: t CK = t CK (I DD); REFRESH
command at every t RFC (I DD) interval; CKE is HIGH,
CS# is HIGH between valid commands; Other control
and address bus inputs are switching; Data bus
inputs are switching
Self refresh current: CK and CK# at 0V; CKE ≤
0.2V; Other control and address bus inputs are
floating; Data bus inputs are floating
Operating bank interleave read
current: All bank interleaving reads, IOUT = 0mA; BL
= 4, CL = CL (IDD), AL = tRCD (IDD) - 1 × tCK (IDD); tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD =
tRCD (IDD); CKE is HIGH, CS# is HIGH between valid
commands; Address bus inputs are stable during deselects;
Data bus inputs are switching; See on page
for details
IDD5 x8 145 140 mA
x16 150 145
IDD6 x8, x16 7 7 mA
IDD6L 5 5
IDD7 x8 210 185 mA
x16 260 230
Notes: 1. I DD specifications are tested after the device is properly initialized. 0°C ≤ T C ≤ +85°C.
2. V DD = 1.8V ±0.1V, V DDQ = 1.8V ±0.1V, V DDL = 1.8V ±0.1V, V REF = V DDQ/2.
3. I DD parameters are specified with ODT disabled.
4. Data bus consists of DQ, DM, DQS, DQS#, RDQS, RDQS#, LDQS, LDQS#, UDQS, and
UDQS#. I DD values must be met with all combinations of EMR bits 10 and 11.
5. Definitions for I DD conditions:
LOW V IN ≤ V IL(AC)max
HIGH VIN ≥ VIH(AC)min Stable Inputs stable at a HIGH or LOW level
Floating Inputs at VREF = VDDQ/2 Switching Inputs changing between HIGH and LOW every other clock cycle (once per
two clocks) for address and control signals
Switching Inputs changing between HIGH and LOW every other data transfer (once
per clock) for DQ signals, not including masks or strobes
6. IDD1, IDD4R, and IDD7 require A12 in EMR to be enabled during testing.
7. The following IDD values must be derated (IDD limits increase) on IT-option and AT-option
devices when operated outside of the range 0°C ≤ TC ≤ 85°C:
When
T C ≤ 0°C
1Gb: x8, x16 Automotive DDR2 SDRAM
Electrical Specifications – I DD Parameters
I DD2P and I DD3P(SLOW) must be derated by 4%; I DD4R and I DD5W must be derated
by 2%; and I DD6 and I DD7 must be derated by 7%
PDF: 09005aef840eff89
1gbddr2_ait_aat.pdf – Rev. C 7/11 EN 25 Micron Technology, Inc. reserves the right to change products or specifications without notice.
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