1Gb: x8, x16 Automotive DDR2 SDRAM - Micron

Table 27: AC Input Test Conditions
Parameter Symbol Min Max Units Notes
Input setup timing measurement reference level address
balls, bank address balls, CS#, RAS#, CAS#, WE#, ODT,
DM, UDM, LDM, and CKE
VRS See Note 2 1, 2, 3, 4
Input hold timing measurement reference level address
balls, bank address balls, CS#, RAS#, CAS#, WE#, ODT,
DM, UDM, LDM, and CKE
Input timing measurement reference level (single-ended)
DQS for x4, x8; UDQS, LDQS for x16
Input timing measurement reference level (differential)
CK, CK# for x4, x8, x16; DQS, DQS# for x4, x8; RDQS,
RDQS# for x8; UDQS, UDQS#, LDQS, LDQS# for x16
1Gb: x8, x16 Automotive DDR2 SDRAM
AC Overshoot/Undershoot Specification
V RH See Note 5 1, 3, 4, 5
V REF(DC) V DDQ × 0.49 V DDQ × 0.51 V 1, 3, 4, 6
V RD V IX(AC) V 1, 3, 7, 8, 9
Notes: 1. All voltages referenced to V SS.
2. Input waveform setup timing ( t IS b) is referenced from the input signal crossing at the
V IH(AC) level for a rising signal and V IL(AC) for a falling signal applied to the device under
test, as shown in Figure 29 (page 64).
3. See Input Slew Rate Derating (page 53).
4. The slew rate for single-ended inputs is measured from DC level to AC level, V IL(DC) to
V IH(AC) on the rising edge and V IL(AC) to V IH(DC) on the falling edge. For signals referenced
to V REF, the valid intersection is where the “tangent” line intersects V REF, as shown in
Figure 22 (page 56), Figure 24 (page 57), Figure 26 (page 62), and Figure 28
(page 63).
5. Input waveform hold ( t IH b) timing is referenced from the input signal crossing at the
V IL(DC) level for a rising signal and V IH(DC) for a falling signal applied to the device under
test, as shown in Figure 29 (page 64).
6. Input waveform setup timing ( t DS) and hold timing ( t DH) for single-ended data strobe is
referenced from the crossing of DQS, UDQS, or LDQS through the Vref level applied to
the device under test, as shown in Figure 31 (page 65).
7. Input waveform setup timing ( t DS) and hold timing ( t DH) when differential data strobe
is enabled is referenced from the cross-point of DQS/DQS#, UDQS/UDQS#, or LDQS/
LDQS#, as shown in Figure 30 (page 64).
8. Input waveform timing is referenced to the crossing point level (V IX) of two input signals
(V TR and V CP) applied to the device under test, where V TR is the true input signal and V CP
is the complementary input signal, as shown in Figure 32 (page 65).
9. The slew rate for differentially ended inputs is measured from twice the DC level to
twice the AC level: 2 × V IL(DC) to 2 × V IH(AC) on the rising edge and 2 × V IL(AC) to 2 ×
V IH(DC) on the falling edge. For example, the CK/CK# would be –250mV to 500mV for CK
rising edge and would be 250mV to –500mV for CK falling edge.
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