1Gb: x8, x16 Automotive DDR2 SDRAM - Micron

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Figure 4: 64 Meg x 16 Functional Block Diagram ODT CKE CK CK# CS# RAS# CAS# WE# A0–A12, BA0–BA2 16 Command decode Control logic Mode registers 16 Address register Refresh counter 13 3 10 13 Rowaddress MUX 2 13 Bank control logic Bank 7 Bank 7 Bank 6 Bank 5 Bank 6 Bank 5 Bank 4 Bank 4 Bank 3 Bank 3 Bank 2 Bank 2 Bank 1 Bank 0 Bank 1 Bank 0 rowaddress latch and decoder 8,192 Memory array (8,192 x 256 x 64) Columnaddress counter/ latch 8 2 Sense amplifier 16,384 I/O gating DM mask logic 256 (x64) Column decoder 64 CK, CK# 64 COL0, COL1 1Gb: x8, x16 Automotive DDR2 SDRAM Functional Block Diagrams 64 Read latch WRITE FIFO and drivers CK out CK in COL0, COL1 16 16 16 16 MUX 16 DATA CK, CK# DLL DRVRS DQS 4 generator UDQS, UDQS# Input registers LDQS, LDQS# 2 2 2 2 8 2 2 2 Mask 2 2 RCVRS 16 16 64 16 16 16 Data 16 16 16 16 4 ODT control Vdd Q sw1 sw2 sw3 sw1 sw2 sw3 R1 R2 R3 R1 R2 R3 sw1 sw2 R1 R1 R2 R2 sw1 sw2 R1 R1 R2 R2 Vss Q sw3 R3 R3 sw3 R3 R3 DQ0–DQ15 UDQS, UDQS# LDQS, LDQS# UDM, LDM PDF: 09005aef840eff89 1gbddr2_ait_aat.pdf – Rev. C 7/11 EN 12 Micron Technology, Inc. reserves the right to change products or specifications without notice. � 2010 Micron Technology, Inc. All rights reserved.
Ball Assignments and Descriptions Figure 5: 60-Ball FBGA – x8 Ball Assignments (Top View) A B C D E F G H J K L 1 NF, DQ6 V DDQ NF, DQ4 V DDL BA2 V SS V DD 2 VSSQ DM, DM/RDQS DQ1 V SSQ V REF CKE BA0 A10 A3 A7 A12 3 V NC, RDQS#/NU DD VSS V DDQ DQ3 V SS WE# BA1 A1 A5 A9 RFU 4 5 6 1Gb: x8, x16 Automotive DDR2 SDRAM Ball Assignments and Descriptions 7 9 VSSQ DQS#/NU VDDQ DQS V DDQ DQ2 V SSDL RAS# CAS# A2 A6 A11 RFU 8 V SSQ DQ0 V SSQ CK CK# CS# A0 A4 A8 A13 NF, DQ7 V DDQ NF, DQ5 PDF: 09005aef840eff89 1gbddr2_ait_aat.pdf – Rev. C 7/11 EN 13 Micron Technology, Inc. reserves the right to change products or specifications without notice. � 2010 Micron Technology, Inc. All rights reserved. V DD ODT V DD V SS
Page 1 and 2: Automotive DDR2 SDRAM MT47H128M8 -
Page 3 and 4: 1Gb: x8, x16 Automotive DDR2 SDRAM
Page 9 and 10: Functional Description Automotive I
Page 11: Functional Block Diagrams The DDR2
Page 15 and 16: Table 3: FBGA 84-Ball - x16 and 60-
Page 17 and 18: Packaging Package Dimensions Figure
Page 19 and 20: FBGA Package Capacitance Table 4: I
Page 21 and 22: Table 6: Temperature Limits Paramet
Page 23 and 24: I DD7 Conditions The detailed timin
Page 25 and 26: Table 10: DDR2 I DD Specifications
Page 27 and 28: PDF: 09005aef840eff89 Micron Techno
Page 39 and 40: AC and DC Operating Conditions Tabl
Page 41 and 42: Input Electrical Characteristics an
Page 45 and 46: Table 19: Output Characteristics Pa
Page 47 and 48: Figure 15: Full Strength Pull-Up Ch
Page 49 and 50: Figure 17: Reduced Strength Pull-Up
Page 51 and 52: AC Overshoot/Undershoot Specificati
Page 53 and 54: Input Slew Rate Derating 1Gb: x8, x
Page 57 and 58: Figure 23: Nominal Slew Rate for t
Page 61 and 62: Table 34: Single-Ended DQS Slew Rat
Page 63 and 64:
Figure 27: Nominal Slew Rate for t
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Figure 31: AC Input Test Signal Wav
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6. Bank addresses (BA) determine wh
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Table 38: Truth Table - Current Sta
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NO OPERATION (NOP) LOAD MODE (LM) A
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Burst Length Figure 33: MR Definiti
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Write Recovery Power-Down Mode 1Gb:
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Extended Mode Register (EMR) Figure
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On-Die Termination (ODT) ODT effect
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Extended Mode Register 2 (EMR2) Fig
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PDF: 09005aef840eff89 Micron Techno
Page 85 and 86:
1Gb: x8, x16 Automotive DDR2 SDRAM
Page 87 and 88:
Figure 42: Multibank Activate Restr
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Figure 43: READ Latency CK# CK Comm
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Figure 45: Nonconsecutive READ Burs
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Figure 48: READ-to-PRECHARGE - BL =
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Figure 50: Bank Read - Without Auto
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Figure 52: x4, x8 Data Output Timin
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Figure 54: Data Output Timing - t A
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Figure 55: Write Burst CK# CK Comma
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Figure 58: WRITE Interrupted by WRI
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Figure 60: WRITE-to-PRECHARGE CK# C
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Figure 62: Bank Write - with Auto P
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Figure 64: Data Input Timing PRECHA
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SELF REFRESH 1Gb: x8, x16 Automotiv
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Power-Down Mode 1Gb: x8, x16 Automo
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Table 43: Truth Table - CKE 1Gb: x8
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Figure 70: WRITE-to-Power-Down or S
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Figure 74: PRECHARGE Command-to-Pow
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Reset CKE Low Anytime 1Gb: x8, x16
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ODT Timing 1Gb: x8, x16 Automotive
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MRS Command to ODT Update Delay Dur
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Figure 83: ODT Turn-On Timing When
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Figure 85: ODT Turn-On Timing When
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1Gb: x8, x16 Automotive DDR2 SDRAM - Micron

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