1Gb: x8, x16 Automotive DDR2 SDRAM - Micron
1Gb: x8, x16 Automotive DDR2 SDRAM - Micron
1Gb: x8, x16 Automotive DDR2 SDRAM - Micron
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Burst Length<br />
Figure 33: MR Definition<br />
Burst length is defined by bits M0–M2, as shown in Figure 33. Read and write accesses<br />
to the <strong>DDR2</strong> <strong>SDRAM</strong> are burst-oriented, with the burst length being programmable to<br />
either four or eight. The burst length determines the maximum number of column locations<br />
that can be accessed for a given READ or WRITE command.<br />
When a READ or WRITE command is issued, a block of columns equal to the burst<br />
length is effectively selected. All accesses for that burst take place within this block,<br />
meaning that the burst will wrap within the block if a boundary is reached. The block is<br />
uniquely selected by A2–Ai when BL = 4 and by A3–Ai when BL = 8 (where Ai is the most<br />
significant column address bit for a given configuration). The remaining (least significant)<br />
address bit(s) is (are) used to select the starting location within the block. The programmed<br />
burst length applies to both read and write bursts.<br />
BA1 BA0 An A12 A11 A10<br />
2<br />
BA2 1<br />
A9 A8 A7 A6 A5 A4 A3 A2 A1 A0<br />
16 15 14 n 12 11 10 9 8 7 6 5 4 3 2 1 0<br />
0 MR 0 PD WR DLL TM CAS# Latency BT Burst Length<br />
M12 PD Mode<br />
0 Fast exit<br />
(normal)<br />
1 Slow exit<br />
(low power)<br />
M7 Mode<br />
0 Normal<br />
1 Test<br />
M8 DLL Reset<br />
0 No<br />
1 Yes<br />
M11 M10 M9 Write Recovery<br />
0 0 0 Reserved<br />
0 0 1 2<br />
0 1 0 3<br />
0 1 1 4<br />
1 0 0 5<br />
1 0 1 6<br />
1 1 0 7<br />
1 1 1 8<br />
M15 M14 Mode Register Definition<br />
0 0 Mode register (MR)<br />
0 1 Extended mode register (EMR)<br />
1 0 Extended mode register (EMR2)<br />
1 1 Extended mode register (EMR3)<br />
M3<br />
0<br />
1<br />
M6 M5 M4<br />
0 0 0<br />
0 0 1<br />
0 1 0<br />
0 1 1<br />
1 0 0<br />
1 0 1<br />
1 1 0<br />
1 1 1<br />
<strong>1Gb</strong>: <strong>x8</strong>, <strong>x16</strong> <strong>Automotive</strong> <strong>DDR2</strong> <strong>SDRAM</strong><br />
Mode Register (MR)<br />
Address Bus<br />
M2 M1 M0 Burst Length<br />
0 0 0 Reserved<br />
0 0 1 Reserved<br />
0 1 0 4<br />
0 1 1 8<br />
1 0 0 Reserved<br />
1 0 1 Reserved<br />
1 1 0 Reserved<br />
1 1 1 Reserved<br />
Burst Type<br />
Sequential<br />
Interleaved<br />
CAS Latency (CL)<br />
Reserved<br />
Reserved<br />
Reserved<br />
3<br />
4<br />
5<br />
6<br />
7<br />
Mode Register (Mx)<br />
Notes: 1. M16 (BA2) is only applicable for densities ≥<strong>1Gb</strong>, reserved for future use, and must be<br />
programmed to “0.”<br />
2. Mode bits (Mn) with corresponding address balls (An) greater than M12 (A12) are reserved<br />
for future use and must be programmed to “0.”<br />
3. Not all listed WR and CL options are supported in any individual speed grade.<br />
PDF: 09005aef840eff89<br />
1gbddr2_ait_aat.pdf – Rev. C 7/11 EN 73 <strong>Micron</strong> Technology, Inc. reserves the right to change products or specifications without notice.<br />
� 2010 <strong>Micron</strong> Technology, Inc. All rights reserved.