1Gb: x8, x16 Automotive DDR2 SDRAM - Micron

Table 30: DDR2-400/533 t DS, t DH Derating Values with Differential Strobe
1Gb: x8, x16 Automotive DDR2 SDRAM
Input Slew Rate Derating
All units are shown in picoseconds
DQ
DQS, DQS# Differential Slew Rate
Slew 4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns 0.8 V/ns
Rate Δ Δ Δ Δ Δ Δ Δ Δ Δ Δ Δ Δ Δ Δ Δ Δ Δ Δ
(V/ns) tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH 2.0 125 45 125 45 125 45 – – – – – – – – – – – –
1.5 83 21 83 21 83 21 95 33 – – – – – – – – – –
1.0 0 0 0 0 0 0 12 12 24 24 – – – – – – – –
0.9 – – –11 –14 –11 –14 1 –2 13 10 25 22 – – – – – –
0.8 – – – – –25 –31 –13 –19 –1 –7 11 5 23 17 – – – –
0.7 – – – – – – –31 –42 –19 –30 –7 –18 5 –6 17 6 – –
0.6 – – – – – – – – –43 –59 –31 –47 –19 –35 –7 –23 5 –11
0.5 – – – – – – – – – – –74 –89 –62 –77 –50 –65 –38 –53
0.4 – – – – – – – – – – – – –127 –140 –115 –128 –103 –116
Notes: 1. For all input signals, the total t DS and t DH required is calculated by adding the data
sheet value to the derating value listed in Table 30.
2. t DS nominal slew rate for a rising signal is defined as the slew rate between the last
crossing of V REF(DC) and the first crossing of V IH(AC)min. t DS nominal slew rate for a falling
signal is defined as the slew rate between the last crossing of V REF(DC) and the first crossing
of V IL(AC)max. If the actual signal is always earlier than the nominal slew rate line between
the shaded “V REF(DC) to AC region,” use the nominal slew rate for the derating
value (see Figure 25 (page 62)). If the actual signal is later than the nominal slew rate
line anywhere between the shaded “V REF(DC) to AC region,” the slew rate of a tangent
line to the actual signal from the AC level to DC level is used for the derating value (see
Figure 26 (page 62)).
3. t DH nominal slew rate for a rising signal is defined as the slew rate between the last
crossing of V IL(DC)max and the first crossing of V REF(DC). t DH nominal slew rate for a falling
signal is defined as the slew rate between the last crossing of V IH(DC)min and the first
crossing of V REF(DC). If the actual signal is always later than the nominal slew rate line
between the shaded “DC level to V REF(DC) region,” use the nominal slew rate for the derating
value (see Figure 27 (page 63)). If the actual signal is earlier than the nominal
slew rate line anywhere between shaded “DC to V REF(DC) region,” the slew rate of a tangent
line to the actual signal from the DC level to V REF(DC) level is used for the derating
value (see Figure 28 (page 63)).
4. Although the total setup time might be negative for slow slew rates (a valid input signal
will not have reached V IH[AC]/V IL[AC] at the time of the rising clock transition), a valid input
signal is still required to complete the transition and reach V IH(AC)/V IL(AC).
5. For slew rates between the values listed in this table, the derating values may be obtained
by linear interpolation.
6. These values are typically not subject to production test. They are verified by design and
characterization.
7. Single-ended DQS requires special derating. The values in Table 32 (page 60) are the
DQS single-ended slew rate derating with DQS referenced at V REF and DQ referenced at
the logic levels t DS b and t DH b. Converting the derated base values from DQ referenced
to the AC/DC trip points to DQ referenced to V REF is listed in Table 34 (page 61) and
Table 35 (page 61). Table 34 provides the V REF-based fully derated values for the DQ
( t DS a and t DH a) for DDR2-533. Table 35 provides the V REF-based fully derated values for
the DQ ( t DS a and t DH a) for DDR2-400.
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