1Gb: x8, x16 Automotive DDR2 SDRAM - Micron
1Gb: x8, x16 Automotive DDR2 SDRAM - Micron
1Gb: x8, x16 Automotive DDR2 SDRAM - Micron
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6. Bank addresses (BA) determine which bank is to be operated upon. BA during a LOAD<br />
MODE command selects which mode register is programmed.<br />
7. SELF REFRESH exit is asynchronous.<br />
8. Burst reads or writes at BL = 4 cannot be terminated or interrupted. See Figure 46<br />
(page 92) and Figure 58 (page 103) for other restrictions and details.<br />
9. The power-down mode does not perform any REFRESH operations. The duration of<br />
power-down is limited by the refresh requirements outlined in the AC parametric section.<br />
Table 37: Truth Table – Current State Bank n – Command to Bank n<br />
Notes: 1–6 apply to the entire table<br />
<strong>1Gb</strong>: <strong>x8</strong>, <strong>x16</strong> <strong>Automotive</strong> <strong>DDR2</strong> <strong>SDRAM</strong><br />
Commands<br />
Current<br />
State CS# RAS# CAS# WE# Command/Action Notes<br />
Any H X X X DESELECT (NOP/continue previous operation)<br />
L H H H NO OPERATION (NOP/continue previous operation)<br />
Idle L L H H ACTIVATE (select and activate row)<br />
L L L H REFRESH 7<br />
L L L L LOAD MODE 7<br />
Row active L H L H READ (select column and start READ burst) 8<br />
L H L L WRITE (select column and start WRITE burst) 8<br />
L L H L PRECHARGE (deactivate row in bank or banks) 9<br />
Read (auto L H L H READ (select column and start new READ burst) 8<br />
precharge L H L L WRITE (select column and start WRITE burst) 8, 10<br />
disabled)<br />
L L H L PRECHARGE (start PRECHARGE) 9<br />
Write<br />
L H L H READ (select column and start READ burst) 8<br />
(auto pre- L H L L WRITE (select column and start new WRITE burst) 8<br />
chargedisabled) L L H L PRECHARGE (start PRECHARGE) 9<br />
Notes: 1. This table applies when CKEn - 1 was HIGH and CKEn is HIGH and after t XSNR has been<br />
met (if the previous state was self refresh).<br />
2. This table is bank-specific, except where noted (the current state is for a specific bank<br />
and the commands shown are those allowed to be issued to that bank when in that<br />
state). Exceptions are covered in the notes below.<br />
3. Current state definitions:<br />
The bank has been precharged,<br />
Idle:<br />
tRP has been met, and any READ burst is complete.<br />
Row A row in the bank has been activated, and<br />
active:<br />
tRCD has been met. No data bursts/<br />
accesses and no register accesses are in progress.<br />
Read: A READ burst has been initiated, with auto precharge disabled and has not yet<br />
terminated.<br />
Write: A WRITE burst has been initiated with auto precharge disabled and has not yet<br />
terminated.<br />
4. The following states must not be interrupted by a command issued to the same bank.<br />
Issue DESELECT or NOP commands, or allowable commands to the other bank, on any<br />
clock edge occurring during these states. Allowable commands to the other bank are<br />
determined by its current state and this table, and according to Table 38 (page 69).<br />
PDF: 09005aef840eff89<br />
1gbddr2_ait_aat.pdf – Rev. C 7/11 EN 67 <strong>Micron</strong> Technology, Inc. reserves the right to change products or specifications without notice.<br />
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