1Gb: x8, x16 Automotive DDR2 SDRAM - Micron

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Figure 51: Bank Read – with Auto Precharge CK# CK CKE Command 1 Address A10 Bank address DM DQS, DQS# DQ 6 T0 T1 T2 T3 T4 T5 T6 T7 T7n T8 T8n RA Case 1: t AC (MIN) and t DQSCK (MIN) Case 2: t AC (MAX) and t DQSCK (MAX) DQS, DQS# DQ 6 NOP 1 ACT tCK tCH tCL tRCD tRAS tRC NOP 1 RA Col n Bank x READ 2,3 4 Bank x AL = 1 4-bit prefetch 1Gb: x8, x16 Automotive DDR2 SDRAM READ NOP 1 NOP 1 NOP 1 NOP 1 NOP 1 tRTP CL = 3 tLZ (MIN) tLZ (MAX) tRP tDQSCK (MIN) tRPST tRPRE 5 5 5 tLZ (MIN) tRPRE tLZ Internal (MAX) precharge DO n tAC (MIN) tDQSCK (MAX) DO n tAC (MAX) Transitioning Data tHZ (MIN) tRPST tHZ (MAX) ACT RA RA Bank x 5 Don’t Care Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid at these times. 2. BL = 4, RL = 4 (AL = 1, CL = 3) in the case shown. 3. The DDR2 SDRAM internally delays auto precharge until both t RAS (MIN) and t RTP (MIN) have been satisfied. 4. Enable auto precharge. 5. I/O balls, when entering or exiting High-Z, are not referenced to a specific voltage level, but to when the device begins to drive or no longer drives, respectively. 6. DO n = data-out from column n; subsequent elements are applied in the programmed order. PDF: 09005aef840eff89 1gbddr2_ait_aat.pdf – Rev. C 7/11 EN 96 Micron Technology, Inc. reserves the right to change products or specifications without notice. � 2010 Micron Technology, Inc. All rights reserved.
Figure 52: x4, x8 Data Output Timing – t DQSQ, t QH, and Data Valid Window CK# CK DQS# DQS3 DQ (last data valid) DQ4 DQ4 DQ4 DQ4 DQ4 DQ4 DQ (first data no longer valid) DQ (last data valid) DQ (first data no longer valid) All DQs and DQS collectively6 Earliest signal transition T1 T2 T2n T3 T3n T4 tHP1 Latest signal transition tHP1 t QH 5 1Gb: x8, x16 Automotive DDR2 SDRAM READ tHP1 tHP1 tHP1 T2 T2 T2 tQH5 tQHS T2n T2n T2n tQH5 tQH5 tQHS tQHS tQHS T3 T3 T3 tHP1 tDQSQ2 tDQSQ2 tDQSQ2 tDQSQ2 Data valid window Data valid window Data valid window T3n T3n T3n Data valid window Notes: 1. t HP is the lesser of t CL or t CH clock transitions collectively when a bank is active. 2. t DQSQ is derived at each DQS clock edge, is not cumulative over time, begins with DQS transitions, and ends with the last valid transition of DQ. 3. DQ transitioning after the DQS transition defines the t DQSQ window. DQS transitions at T2 and at T2n are “early DQS,” at T3 are “nominal DQS,” and at T3n are “late DQS.” 4. DQ0, DQ1, DQ2, DQ3 for x4 or DQ[7:0] for x8. 5. t QH is derived from t HP: t QH = t HP - t QHS. 6. The data valid window is derived for each DQS transition and is defined as t QH - t DQSQ. PDF: 09005aef840eff89 1gbddr2_ait_aat.pdf – Rev. C 7/11 EN 97 Micron Technology, Inc. reserves the right to change products or specifications without notice. � 2010 Micron Technology, Inc. All rights reserved.
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Automotive DDR2 SDRAM MT47H128M8 -
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1Gb: x8, x16 Automotive DDR2 SDRAM
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Functional Description Automotive I
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Functional Block Diagrams The DDR2
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Ball Assignments and Descriptions F
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Table 3: FBGA 84-Ball - x16 and 60-
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Packaging Package Dimensions Figure
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FBGA Package Capacitance Table 4: I
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Table 6: Temperature Limits Paramet
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I DD7 Conditions The detailed timin
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Table 10: DDR2 I DD Specifications
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PDF: 09005aef840eff89 Micron Techno
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AC and DC Operating Conditions Tabl
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Input Electrical Characteristics an
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Page 45 and 46: Table 19: Output Characteristics Pa
Page 47 and 48: Figure 15: Full Strength Pull-Up Ch
Page 49 and 50: Figure 17: Reduced Strength Pull-Up
Page 51 and 52: AC Overshoot/Undershoot Specificati
Page 53 and 54: Input Slew Rate Derating 1Gb: x8, x
Page 55 and 56: 1Gb: x8, x16 Automotive DDR2 SDRAM
Page 57 and 58: Figure 23: Nominal Slew Rate for t
Page 61 and 62: Table 34: Single-Ended DQS Slew Rat
Page 63 and 64: Figure 27: Nominal Slew Rate for t
Page 65 and 66: Figure 31: AC Input Test Signal Wav
Page 67 and 68: 6. Bank addresses (BA) determine wh
Page 69 and 70: Table 38: Truth Table - Current Sta
Page 71 and 72: NO OPERATION (NOP) LOAD MODE (LM) A
Page 73 and 74: Burst Length Figure 33: MR Definiti
Page 75 and 76: Write Recovery Power-Down Mode 1Gb:
Page 77 and 78: Extended Mode Register (EMR) Figure
Page 79 and 80: On-Die Termination (ODT) ODT effect
Page 81 and 82: Extended Mode Register 2 (EMR2) Fig
Page 83 and 84: PDF: 09005aef840eff89 Micron Techno
Page 87 and 88: Figure 42: Multibank Activate Restr
Page 89 and 90: Figure 43: READ Latency CK# CK Comm
Page 91 and 92: Figure 45: Nonconsecutive READ Burs
Page 93 and 94: Figure 48: READ-to-PRECHARGE - BL =
Page 95: Figure 50: Bank Read - Without Auto
Page 99 and 100: Figure 54: Data Output Timing - t A
Page 101 and 102: Figure 55: Write Burst CK# CK Comma
Page 103 and 104: Figure 58: WRITE Interrupted by WRI
Page 105 and 106: Figure 60: WRITE-to-PRECHARGE CK# C
Page 107 and 108: Figure 62: Bank Write - with Auto P
Page 109 and 110: Figure 64: Data Input Timing PRECHA
Page 111 and 112: SELF REFRESH 1Gb: x8, x16 Automotiv
Page 113 and 114: Power-Down Mode 1Gb: x8, x16 Automo
Page 115 and 116: Table 43: Truth Table - CKE 1Gb: x8
Page 117 and 118: Figure 70: WRITE-to-Power-Down or S
Page 119 and 120: Figure 74: PRECHARGE Command-to-Pow
Page 121 and 122: Reset CKE Low Anytime 1Gb: x8, x16
Page 123 and 124: ODT Timing 1Gb: x8, x16 Automotive
Page 125 and 126: MRS Command to ODT Update Delay Dur
Page 127 and 128: Figure 83: ODT Turn-On Timing When
Page 129: Figure 85: ODT Turn-On Timing When
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1Gb: x8, x16 Automotive DDR2 SDRAM - Micron

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