1Gb: x8, x16 Automotive DDR2 SDRAM - Micron
1Gb: x8, x16 Automotive DDR2 SDRAM - Micron
1Gb: x8, x16 Automotive DDR2 SDRAM - Micron
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PRECHARGE<br />
REFRESH<br />
SELF REFRESH<br />
Mode Register (MR)<br />
<strong>1Gb</strong>: <strong>x8</strong>, <strong>x16</strong> <strong>Automotive</strong> <strong>DDR2</strong> <strong>SDRAM</strong><br />
Mode Register (MR)<br />
The PRECHARGE command is used to deactivate the open row in a particular bank or<br />
the open row in all banks. The bank(s) will be available for a subsequent row activation<br />
a specified time ( t RP) after the PRECHARGE command is issued, except in the case of<br />
concurrent auto precharge, where a READ or WRITE command to a different bank is allowed<br />
as long as it does not interrupt the data transfer in the current bank and does not<br />
violate any other timing parameters. After a bank has been precharged, it is in the idle<br />
state and must be activated prior to any READ or WRITE commands being issued to<br />
that bank. A PRECHARGE command is allowed if there is no open row in that bank (idle<br />
state) or if the previously open row is already in the process of precharging. However,<br />
the precharge period will be determined by the last PRECHARGE command issued to<br />
the bank.<br />
REFRESH is used during normal operation of the <strong>DDR2</strong> <strong>SDRAM</strong> and is analogous to<br />
CAS#-before-RAS# (CBR) REFRESH. All banks must be in the idle mode prior to issuing<br />
a REFRESH command. This command is nonpersistent, so it must be issued each time<br />
a refresh is required. The addressing is generated by the internal refresh controller. This<br />
makes the address bits a “Don’t Care” during a REFRESH command.<br />
The SELF REFRESH command can be used to retain data in the <strong>DDR2</strong> <strong>SDRAM</strong>, even if<br />
the rest of the system is powered down. When in the self refresh mode, the <strong>DDR2</strong><br />
<strong>SDRAM</strong> retains data without external clocking. All power supply inputs (including Vref)<br />
must be maintained at valid levels upon entry/exit and during SELF REFRESH operation.<br />
The SELF REFRESH command is initiated like a REFRESH command except CKE is<br />
LOW. The DLL is automatically disabled upon entering self refresh and is automatically<br />
enabled upon exiting self refresh.<br />
The mode register is used to define the specific mode of operation of the <strong>DDR2</strong> <strong>SDRAM</strong>.<br />
This definition includes the selection of a burst length, burst type, CAS latency, operating<br />
mode, DLL RESET, write recovery, and power-down mode, as shown in Figure 33<br />
(page 73). Contents of the mode register can be altered by re-executing the LOAD<br />
MODE (LM) command. If the user chooses to modify only a subset of the MR variables,<br />
all variables must be programmed when the command is issued.<br />
The MR is programmed via the LM command and will retain the stored information until<br />
it is programmed again or until the device loses power (except for bit M8, which is<br />
self-clearing). Reprogramming the mode register will not alter the contents of the memory<br />
array, provided it is performed correctly.<br />
The LM command can only be issued (or reissued) when all banks are in the precharged<br />
state (idle state) and no bursts are in progress. The controller must wait the specified<br />
time tMRD before initiating any subsequent operations such as an ACTIVATE command.<br />
Violating either of these requirements will result in an unspecified operation.<br />
PDF: 09005aef840eff89<br />
1gbddr2_ait_aat.pdf – Rev. C 7/11 EN 72 <strong>Micron</strong> Technology, Inc. reserves the right to change products or specifications without notice.<br />
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