1Gb: x8, x16 Automotive DDR2 SDRAM - Micron

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Figure 25: Nominal Slew Rate for t DS DQS1 DQS#1 V DDQ V IH(AC)min V IH(DC)min V REF(DC) V IL(DC)max V IL(AC)max V SS Figure 26: Tangent Line for t DS V REF to AC region Setup slew rate falling signal t DS Nominal slew rate t DH �TF �TR VREF(DC) - VIL(AC)max = �TF Setup slew rate rising signal t DS Nominal slew rate t DH V REF to AC region VIH(AC)min - VREF(DC) = �TR Note: 1. DQS, DQS# signals must be monotonic between V IL(DC)max and V IH(DC)min. DQS 1 DQS# 1 V DDQ V IH(AC)min V IH(DC)min V REF(DC) V IL(DC)max V IL(AC)max V SS Setup slew rate falling signal V REF to AC region t DS Tangent line Nominal line t DH �TF �TR Tangent line (VREF[DC] - VIL[AC]max ) = �TF Nominal line Setup slew rate rising signal 1Gb: x8, x16 Automotive DDR2 SDRAM Input Slew Rate Derating t DS t DH Tangent line V REF to AC region Tangent line (VIH[AC]min - VREF[DC] ) = �TR Note: 1. DQS, DQS# signals must be monotonic between V IL(DC)max and V IH(DC)min. PDF: 09005aef840eff89 1gbddr2_ait_aat.pdf – Rev. C 7/11 EN 62 Micron Technology, Inc. reserves the right to change products or specifications without notice. � 2010 Micron Technology, Inc. All rights reserved.
Figure 27: Nominal Slew Rate for t DH DQS1 DQS#1 V DDQ V IH(AC)min V IH(DC)min V REF(DC) V IL(DC)max V IL(AC)max V SS Figure 28: Tangent Line for t DH DC to V REF region Hold slew rate = rising signal t IS t IH Nominal slew rate DC to V REF region V REF(DC) - V IL(DC)max �TR �TR �TF Hold slew rate falling signal t IS Nominal slew rate = t IH V IH(DC)min - V REF(DC) �TF Note: 1. DQS, DQS# signals must be monotonic between V IL(DC)max and V IH(DC)min. DQS1 DQS#1 V DDQ V IH(AC)min V IH(DC)min V REF(DC) V IL(DC)max V IL(AC)max V SS Hold slew rate rising signal DC to V REF region t IS Tangent line t IH 1Gb: x8, x16 Automotive DDR2 SDRAM Input Slew Rate Derating Nominal line t IS Tangent line t IH DC to V REF region Nominal line �TR �TF Tangent line (VREF[DC] - VIL[DC]max ) = �TR Hold slew rate Tangent line (VIH[DC]min - VREF[DC] ) = falling signal �TF Note: 1. DQS, DQS# signals must be monotonic between V IL(DC)max and V IH(DC)min. PDF: 09005aef840eff89 1gbddr2_ait_aat.pdf – Rev. C 7/11 EN 63 Micron Technology, Inc. reserves the right to change products or specifications without notice. � 2010 Micron Technology, Inc. All rights reserved.
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Automotive DDR2 SDRAM MT47H128M8 -
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1Gb: x8, x16 Automotive DDR2 SDRAM
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Functional Description Automotive I
Page 11 and 12: Functional Block Diagrams The DDR2
Page 13 and 14: Ball Assignments and Descriptions F
Page 15 and 16: Table 3: FBGA 84-Ball - x16 and 60-
Page 17 and 18: Packaging Package Dimensions Figure
Page 19 and 20: FBGA Package Capacitance Table 4: I
Page 21 and 22: Table 6: Temperature Limits Paramet
Page 23 and 24: I DD7 Conditions The detailed timin
Page 25 and 26: Table 10: DDR2 I DD Specifications
Page 27 and 28: PDF: 09005aef840eff89 Micron Techno
Page 39 and 40: AC and DC Operating Conditions Tabl
Page 41 and 42: Input Electrical Characteristics an
Page 43 and 44: 1Gb: x8, x16 Automotive DDR2 SDRAM
Page 45 and 46: Table 19: Output Characteristics Pa
Page 47 and 48: Figure 15: Full Strength Pull-Up Ch
Page 49 and 50: Figure 17: Reduced Strength Pull-Up
Page 51 and 52: AC Overshoot/Undershoot Specificati
Page 53 and 54: Input Slew Rate Derating 1Gb: x8, x
Page 57 and 58: Figure 23: Nominal Slew Rate for t
Page 61: Table 34: Single-Ended DQS Slew Rat
Page 65 and 66: Figure 31: AC Input Test Signal Wav
Page 67 and 68: 6. Bank addresses (BA) determine wh
Page 69 and 70: Table 38: Truth Table - Current Sta
Page 71 and 72: NO OPERATION (NOP) LOAD MODE (LM) A
Page 73 and 74: Burst Length Figure 33: MR Definiti
Page 75 and 76: Write Recovery Power-Down Mode 1Gb:
Page 77 and 78: Extended Mode Register (EMR) Figure
Page 79 and 80: On-Die Termination (ODT) ODT effect
Page 81 and 82: Extended Mode Register 2 (EMR2) Fig
Page 87 and 88: Figure 42: Multibank Activate Restr
Page 89 and 90: Figure 43: READ Latency CK# CK Comm
Page 91 and 92: Figure 45: Nonconsecutive READ Burs
Page 93 and 94: Figure 48: READ-to-PRECHARGE - BL =
Page 95 and 96: Figure 50: Bank Read - Without Auto
Page 97 and 98: Figure 52: x4, x8 Data Output Timin
Page 99 and 100: Figure 54: Data Output Timing - t A
Page 101 and 102: Figure 55: Write Burst CK# CK Comma
Page 103 and 104: Figure 58: WRITE Interrupted by WRI
Page 105 and 106: Figure 60: WRITE-to-PRECHARGE CK# C
Page 107 and 108: Figure 62: Bank Write - with Auto P
Page 109 and 110: Figure 64: Data Input Timing PRECHA
Page 111 and 112: SELF REFRESH 1Gb: x8, x16 Automotiv
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Power-Down Mode 1Gb: x8, x16 Automo
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Table 43: Truth Table - CKE 1Gb: x8
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Figure 70: WRITE-to-Power-Down or S
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Figure 74: PRECHARGE Command-to-Pow
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Reset CKE Low Anytime 1Gb: x8, x16
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ODT Timing 1Gb: x8, x16 Automotive
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MRS Command to ODT Update Delay Dur
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Figure 83: ODT Turn-On Timing When
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Figure 85: ODT Turn-On Timing When
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1Gb: x8, x16 Automotive DDR2 SDRAM - Micron

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