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1Gb: x8, x16 Automotive DDR2 SDRAM - Micron

1Gb: x8, x16 Automotive DDR2 SDRAM - Micron

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READ with auto<br />

precharge enabled/<br />

WRITE with auto<br />

precharge enabled:<br />

The READ with auto precharge enabled or WRITE with auto precharge<br />

enabled states can each be broken into two parts: the access<br />

period and the precharge period. For READ with auto precharge,<br />

the precharge period is defined as if the same burst was<br />

executed with auto precharge disabled and then followed with<br />

the earliest possible PRECHARGE command that still accesses all<br />

of the data in the burst. For WRITE with auto precharge, the precharge<br />

period begins when t WR ends, with t WR measured as if<br />

auto precharge was disabled. The access period starts with registration<br />

of the command and ends where the precharge period<br />

(or t RP) begins. This device supports concurrent auto precharge<br />

such that when a READ with auto precharge is enabled or a<br />

WRITE with auto precharge is enabled, any command to other<br />

banks is allowed, as long as that command does not interrupt<br />

the read or write data transfer already in process. In either case,<br />

all other related limitations apply (contention between read data<br />

and write data must be avoided).<br />

The minimum delay from a READ or WRITE command with auto precharge enabled to<br />

a command to a different bank is summarized in Table 39 (page 70).<br />

4. REFRESH and LOAD MODE commands may only be issued when all banks are idle.<br />

5. Not used.<br />

6. All states and sequences not shown are illegal or reserved.<br />

7. READs or WRITEs listed in the Command/Action column include READs or WRITEs with<br />

auto precharge enabled and READs or WRITEs with auto precharge disabled.<br />

8. A WRITE command may be applied after the completion of the READ burst.<br />

9. Requires appropriate DM.<br />

10. The number of clock cycles required to meet tWTR is either two or tWTR/ tCK, whichever<br />

is greater.<br />

Table 39: Minimum Delay with Auto Precharge Enabled<br />

From Command (Bank n) To Command (Bank m)<br />

Minimum Delay<br />

(with Concurrent Auto Precharge) Units<br />

WRITE with auto precharge READ or READ with auto precharge (CL - 1) + (BL/2) + tWTR tCK WRITE or WRITE with auto precharge (BL/2) tCK PRECHARGE or ACTIVATE 1 tCK READ with auto precharge READ or READ with auto precharge (BL/2) tCK WRITE or WRITE with auto precharge (BL/2) + 2 tCK PRECHARGE or ACTIVATE 1 tCK DESELECT<br />

<strong>1Gb</strong>: <strong>x8</strong>, <strong>x16</strong> <strong>Automotive</strong> <strong>DDR2</strong> <strong>SDRAM</strong><br />

Commands<br />

The DESELECT function (CS# HIGH) prevents new commands from being executed by<br />

the <strong>DDR2</strong> <strong>SDRAM</strong>. The <strong>DDR2</strong> <strong>SDRAM</strong> is effectively deselected. Operations already in<br />

progress are not affected. DESELECT is also referred to as COMMAND INHIBIT.<br />

PDF: 09005aef840eff89<br />

1gbddr2_ait_aat.pdf – Rev. C 7/11 EN 70 <strong>Micron</strong> Technology, Inc. reserves the right to change products or specifications without notice.<br />

� 2010 <strong>Micron</strong> Technology, Inc. All rights reserved.

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