1Gb: x8, x16 Automotive DDR2 SDRAM - Micron

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Figure 53: x16 Data Output Timing – t DQSQ, t QH, and Data Valid Window CK# CK LDSQ# LDQS 3 DQ (last data valid) 4 DQ4 DQ4 DQ4 DQ4 DQ4 DQ4 DQ (first data no longer valid) 4 DQ (last data valid) 4 DQ (first data no longer valid) 4 DQ0–DQ7 and LDQS collectively 6 UDQS# UDQS 3 DQ (last data valid) 7 DQ7 DQ7 DQ7 DQ7 DQ7 DQ7 DQ (first data no longer valid) 7 DQ (last data valid) 7 DQ (first data no longer valid) 7 DQ8–DQ15 and UDQS collectively 6 T1 T2 T2n T3 T3n T4 t HP 1 t HP 1 t DQSQ 2 t DQSQ 2 t DQSQ 2 t DQSQ 2 t QH 5 T2 T2 T2 Data valid window t DQSQ 2 t HP 1 t HP 1 t HP 1 t HP 1 T2 T2 T2 T2n T2n T2n Data valid window T2n T2n T2n tQH5 tQH5 tQHS tQHS tQH5 tQH5 tQH5 tQH5 tQHS tQHS tQHS Data valid window 1Gb: x8, x16 Automotive DDR2 SDRAM READ tQH5 tQHS T3 T3 T3 t DQSQ 2 t DQSQ 2 t DQSQ 2 Data valid window Data valid window T3 T3 T3 Data valid window T3n T3n T3n Data valid window T3n T3n T3n Data valid window Notes: 1. t HP is the lesser of t CL or t CH clock transitions collectively when a bank is active. 2. t DQSQ is derived at each DQS clock edge, is not cumulative over time, begins with DQS transitions, and ends with the last valid transition of DQ. 3. DQ transitioning after the DQS transitions define the t DQSQ window. LDQS defines the lower byte, and UDQS defines the upper byte. 4. DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, or DQ7. PDF: 09005aef840eff89 1gbddr2_ait_aat.pdf – Rev. C 7/11 EN 98 Micron Technology, Inc. reserves the right to change products or specifications without notice. � 2010 Micron Technology, Inc. All rights reserved. t QHS t QHS Lower Byte Upper Byte
Figure 54: Data Output Timing – t AC and t DQSCK WRITE DQS#/DQS or LDQS#/LDQS/UDQ#/UDQS 3 DQ (last data valid) DQ (first data valid) All DQs collectively4 5. t QH is derived from t HP: t QH = t HP - t QHS. 6. The data valid window is derived for each DQS transition and is t QH - t DQSQ. 7. DQ8, DQ9, DQ10, D11, DQ12, DQ13, DQ14, or DQ15. CK# CK T01 T1 T2 T3 T3n T4 T4n T5 T5n T6 T6n T7 t LZ (MIN) t RPRE t LZ (MIN) 1Gb: x8, x16 Automotive DDR2 SDRAM WRITE t DQSCK 2 (MIN) T3 T3 t AC 5 (MIN) t AC 5 (MAX) tHZ (MAX) tDQSCK2 (MAX) tRPST T3n T4 T4n T5 T5n T6 T6n T3n T4 T4n T5n T3 T3n T4 T4n T5 T5n T6 T5 T6 T6n T6n t HZ (MAX) Notes: 1. READ command with CL = 3, AL = 0 issued at T0. 2. t DQSCK is the DQS output window relative to CK and is the long-term component of DQS skew. 3. DQ transitioning after DQS transitions define t DQSQ window. 4. All DQ must transition by t DQSQ after DQS transitions, regardless of t AC. 5. t AC is the DQ output window relative to CK and is the “long term” component of DQ skew. 6. t LZ (MIN) and t AC (MIN) are the first valid signal transitions. 7. t HZ (MAX) and t AC (MAX) are the latest valid signal transitions. 8. I/O balls, when entering or exiting High-Z, are not referenced to a specific voltage level, but to when the device begins to drive or no longer drives, respectively. WRITE bursts are initiated with a WRITE command. DDR2 SDRAM uses WL equal to RL minus one clock cycle (WL = RL - 1CK) (see READ (page 71)). The starting column and bank addresses are provided with the WRITE command, and auto precharge is either enabled or disabled for that access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst. Note: For the WRITE commands used in the following illustrations, auto precharge is disabled. During WRITE bursts, the first valid data-in element will be registered on the first rising edge of DQS following the WRITE command, and subsequent data elements will be registered on successive edges of DQS. The LOW state on DQS between the WRITE command and the first rising edge is known as the write preamble; the LOW state on DQS following the last data-in element is known as the write postamble. The time between the WRITE command and the first rising DQS edge is WL ± tDQSS. Subsequent DQS positive rising edges are timed, relative to the associated clock edge, as PDF: 09005aef840eff89 1gbddr2_ait_aat.pdf – Rev. C 7/11 EN 99 Micron Technology, Inc. reserves the right to change products or specifications without notice. � 2010 Micron Technology, Inc. All rights reserved.
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Automotive DDR2 SDRAM MT47H128M8 -
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1Gb: x8, x16 Automotive DDR2 SDRAM
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Functional Description Automotive I
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Functional Block Diagrams The DDR2
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Ball Assignments and Descriptions F
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Table 3: FBGA 84-Ball - x16 and 60-
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Packaging Package Dimensions Figure
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FBGA Package Capacitance Table 4: I
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Table 6: Temperature Limits Paramet
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I DD7 Conditions The detailed timin
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Table 10: DDR2 I DD Specifications
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PDF: 09005aef840eff89 Micron Techno
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AC and DC Operating Conditions Tabl
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Input Electrical Characteristics an
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Table 19: Output Characteristics Pa
Page 47 and 48: Figure 15: Full Strength Pull-Up Ch
Page 49 and 50: Figure 17: Reduced Strength Pull-Up
Page 51 and 52: AC Overshoot/Undershoot Specificati
Page 53 and 54: Input Slew Rate Derating 1Gb: x8, x
Page 55 and 56: 1Gb: x8, x16 Automotive DDR2 SDRAM
Page 57 and 58: Figure 23: Nominal Slew Rate for t
Page 61 and 62: Table 34: Single-Ended DQS Slew Rat
Page 63 and 64: Figure 27: Nominal Slew Rate for t
Page 65 and 66: Figure 31: AC Input Test Signal Wav
Page 67 and 68: 6. Bank addresses (BA) determine wh
Page 69 and 70: Table 38: Truth Table - Current Sta
Page 71 and 72: NO OPERATION (NOP) LOAD MODE (LM) A
Page 73 and 74: Burst Length Figure 33: MR Definiti
Page 75 and 76: Write Recovery Power-Down Mode 1Gb:
Page 77 and 78: Extended Mode Register (EMR) Figure
Page 79 and 80: On-Die Termination (ODT) ODT effect
Page 81 and 82: Extended Mode Register 2 (EMR2) Fig
Page 83 and 84: PDF: 09005aef840eff89 Micron Techno
Page 87 and 88: Figure 42: Multibank Activate Restr
Page 89 and 90: Figure 43: READ Latency CK# CK Comm
Page 91 and 92: Figure 45: Nonconsecutive READ Burs
Page 93 and 94: Figure 48: READ-to-PRECHARGE - BL =
Page 95 and 96: Figure 50: Bank Read - Without Auto
Page 97: Figure 52: x4, x8 Data Output Timin
Page 101 and 102: Figure 55: Write Burst CK# CK Comma
Page 103 and 104: Figure 58: WRITE Interrupted by WRI
Page 105 and 106: Figure 60: WRITE-to-PRECHARGE CK# C
Page 107 and 108: Figure 62: Bank Write - with Auto P
Page 109 and 110: Figure 64: Data Input Timing PRECHA
Page 111 and 112: SELF REFRESH 1Gb: x8, x16 Automotiv
Page 113 and 114: Power-Down Mode 1Gb: x8, x16 Automo
Page 115 and 116: Table 43: Truth Table - CKE 1Gb: x8
Page 117 and 118: Figure 70: WRITE-to-Power-Down or S
Page 119 and 120: Figure 74: PRECHARGE Command-to-Pow
Page 121 and 122: Reset CKE Low Anytime 1Gb: x8, x16
Page 123 and 124: ODT Timing 1Gb: x8, x16 Automotive
Page 125 and 126: MRS Command to ODT Update Delay Dur
Page 127 and 128: Figure 83: ODT Turn-On Timing When
Page 129: Figure 85: ODT Turn-On Timing When
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1Gb: x8, x16 Automotive DDR2 SDRAM - Micron

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