1Gb: x8, x16 Automotive DDR2 SDRAM - Micron

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Automotive Temperature General Notes 1Gb: x8, x16 Automotive DDR2 SDRAM Functional Description The automotive temperature (AAT) option, if offered, has two simultaneous requirements: ambient temperature surrounding the device cannot be less than –40°C or greater than +105°C, and the case temperature cannot be less than –40°C or greater than +105°C. JEDEC specifications require the refresh rate to double when T C exceeds +85°C; this also requires use of the high-temperature self refresh option. Additionally, ODT resistance, the input/output impedance, and I DD values must be derated when T C is < 0°C or > +85°C. • The functionality and the timing specifications discussed in this data sheet are for the DLL-enabled mode of operation. • Throughout the data sheet, the various figures and text refer to DQs as “DQ.” The DQ term is to be interpreted as any and all DQ collectively, unless specifically stated otherwise. Additionally, the x16 is divided into 2 bytes: the lower byte and the upper byte. For the lower byte (DQ0–DQ7), DM refers to LDM and DQS refers to LDQS. For the upper byte (DQ8–DQ15), DM refers to UDM and DQS refers to UDQS. • A x16 device's DQ bus is comprised of two bytes. If only one of the bytes needs to be used, use the lower byte for data transfers and terminate the upper byte as noted: – Connect UDQS to ground via 1kΩ* resistor – Connect UDQS# to VDD via 1kΩ* resistor – Connect UDM to VDD via 1kΩ* resistor – Connect DQ[15:8] individually to either VSS or VDD via 1kΩ* resistors, or float DQ[15:8]. *If ODT is used, 1kΩ resistor should be changed to 4x that of the selected ODT. • Complete functionality is described throughout the document, and any page or diagram may have been simplified to convey a topic and may not be inclusive of all requirements. • Any specific requirement takes precedence over a general statement. PDF: 09005aef840eff89 1gbddr2_ait_aat.pdf – Rev. C 7/11 EN 10 Micron Technology, Inc. reserves the right to change products or specifications without notice. � 2010 Micron Technology, Inc. All rights reserved.
Functional Block Diagrams The DDR2 SDRAM is a high-speed CMOS, dynamic random access memory. It is internally configured as a multibank DRAM. Figure 3: 128 Meg x 8 Functional Block Diagram ODT CKE CK CK# CS# RAS# CAS# WE# A0–A13, BA0–BA2 17 Command decode Control logic Mode registers 17 Address register Refresh counter 14 3 10 14 Rowaddress MUX 2 14 Bank control logic Bank 0 rowaddress latch 16,384 and decoder Columnaddress counter/ latch Bank 7 Bank 6 Bank 5 Bank 4 Bank 3 Bank 2 Bank 1 8 2 Bank 7 Bank 6 Bank 5 Bank 4 Bank 3 Bank 2 Bank 1 Bank 0 Memory array (16,384 x 256 x 32) Sense amplifers 8,192 I/O gating DM mask logic 256 (x32) Column decoder 1Gb: x8, x16 Automotive DDR2 SDRAM Functional Block Diagrams 32 CK,CK# 32 COL0, COL1 32 Read latch WRITE FIFO and drivers CK out CK in 8 8 8 8 COL0, COL1 MUX 8 Data CK, CK# DLL DRVRS DQS 2 generator UDQS, UDQS# Input LDQS, LDQS# registers 2 2 2 2 4 2 2 2 Mask 2 2 RCVRS 8 8 32 8 8 8 Data 8 8 8 8 2 ODT control Vdd Q sw1 sw2 sw3 sw1 sw2 sw3 R1 R2 R3 R1 R2 R3 sw1 sw2 R1 R1 R2 R2 sw1 sw2 R1 R1 R2 R2 Vss Q sw3 R3 R3 R3 R3 DQ0–DQ7 DQS, DQS# PDF: 09005aef840eff89 1gbddr2_ait_aat.pdf – Rev. C 7/11 EN 11 Micron Technology, Inc. reserves the right to change products or specifications without notice. � 2010 Micron Technology, Inc. All rights reserved. sw3 RDQS# RDQS DM
Page 1 and 2: Automotive DDR2 SDRAM MT47H128M8 -
Page 3 and 4: 1Gb: x8, x16 Automotive DDR2 SDRAM
Page 9: Functional Description Automotive I
Page 13 and 14: Ball Assignments and Descriptions F
Page 15 and 16: Table 3: FBGA 84-Ball - x16 and 60-
Page 17 and 18: Packaging Package Dimensions Figure
Page 19 and 20: FBGA Package Capacitance Table 4: I
Page 21 and 22: Table 6: Temperature Limits Paramet
Page 23 and 24: I DD7 Conditions The detailed timin
Page 25 and 26: Table 10: DDR2 I DD Specifications
Page 27 and 28: PDF: 09005aef840eff89 Micron Techno
Page 39 and 40: AC and DC Operating Conditions Tabl
Page 41 and 42: Input Electrical Characteristics an
Page 45 and 46: Table 19: Output Characteristics Pa
Page 47 and 48: Figure 15: Full Strength Pull-Up Ch
Page 49 and 50: Figure 17: Reduced Strength Pull-Up
Page 51 and 52: AC Overshoot/Undershoot Specificati
Page 53 and 54: Input Slew Rate Derating 1Gb: x8, x
Page 57 and 58: Figure 23: Nominal Slew Rate for t
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Table 34: Single-Ended DQS Slew Rat
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Figure 27: Nominal Slew Rate for t
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Figure 31: AC Input Test Signal Wav
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6. Bank addresses (BA) determine wh
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Table 38: Truth Table - Current Sta
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NO OPERATION (NOP) LOAD MODE (LM) A
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Burst Length Figure 33: MR Definiti
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Write Recovery Power-Down Mode 1Gb:
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Extended Mode Register (EMR) Figure
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On-Die Termination (ODT) ODT effect
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Extended Mode Register 2 (EMR2) Fig
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PDF: 09005aef840eff89 Micron Techno
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1Gb: x8, x16 Automotive DDR2 SDRAM
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Figure 42: Multibank Activate Restr
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Figure 43: READ Latency CK# CK Comm
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Figure 45: Nonconsecutive READ Burs
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Figure 48: READ-to-PRECHARGE - BL =
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Figure 50: Bank Read - Without Auto
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Figure 52: x4, x8 Data Output Timin
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Figure 54: Data Output Timing - t A
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Figure 55: Write Burst CK# CK Comma
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Figure 58: WRITE Interrupted by WRI
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Figure 60: WRITE-to-PRECHARGE CK# C
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Figure 62: Bank Write - with Auto P
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Figure 64: Data Input Timing PRECHA
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SELF REFRESH 1Gb: x8, x16 Automotiv
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Power-Down Mode 1Gb: x8, x16 Automo
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Table 43: Truth Table - CKE 1Gb: x8
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Figure 70: WRITE-to-Power-Down or S
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Figure 74: PRECHARGE Command-to-Pow
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Reset CKE Low Anytime 1Gb: x8, x16
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ODT Timing 1Gb: x8, x16 Automotive
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MRS Command to ODT Update Delay Dur
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Figure 83: ODT Turn-On Timing When
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Figure 85: ODT Turn-On Timing When
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1Gb: x8, x16 Automotive DDR2 SDRAM - Micron

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