1Gb: x8, x16 Automotive DDR2 SDRAM - Micron

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Extended Mode Register 3 (EMR3) Figure 39: EMR3 Definition The extended mode register 3 (EMR3) controls functions beyond those controlled by the mode register. Currently all bits in EMR3 are reserved, as shown in Figure 39. The EMR3 is programmed via the LM command and will retain the stored information until it is programmed again or until the device loses power. Reprogramming the EMR will not alter the contents of the memory array, provided it is performed correctly. EMR3 must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time tMRD before initiating any subsequent operation. Violating either of these requirements could result in an unspecified operation. BA1 BA0 An A12 A11 A10 2 BA2 1 16 0 E15 E14 Mode Register Set 0 0 Mode register (MR) 0 1 Extended mode register (EMR) 1 0 Extended mode register (EMR2) 1 1 Extended mode register (EMR3) A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 15 14 n 12 11 10 9 8 7 6 5 4 3 2 1 0 MRS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1Gb: x8, x16 Automotive DDR2 SDRAM Extended Mode Register 3 (EMR3) Address bus Extended mode register (Ex) Notes: 1. E16 (BA2) is only applicable for densities ≥1Gb, is reserved for future use, and must be programmed to “0.” 2. Mode bits (En) with corresponding address balls (An) greater than E12 (A12) are reserved for future use and must be programmed to “0.” PDF: 09005aef840eff89 1gbddr2_ait_aat.pdf – Rev. C 7/11 EN 82 Micron Technology, Inc. reserves the right to change products or specifications without notice. � 2010 Micron Technology, Inc. All rights reserved.
PDF: 09005aef840eff89 Micron Technology, Inc. reserves the right to change products or specifications without notice. 1gbddr2_ait_aat.pdf – Rev. C 7/11 EN 83 � 2010 Micron Technology, Inc. All rights reserved. Initialization Figure 40: DDR2 Power-Up and Initialization DDR2 SDRAM must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Figure 40 illustrates, and the notes outline, the sequence required for power-up and initialization. V DD V DDL V DDQ V TT 1 V REF CK# CK CKE ODT DM 15 Address 16 Rtt t VTD 1 LVCMOS low level 2 15 High-Z DQS High-Z T0 Ta0 tCK tCL tCL Command NOP 3 PRE DQ 15 High-Z SSTL_18 low level 2 T = 200μs (MIN) 3 Power-up: V DD and stable clock (CK, CK#) Tb0 A10 = 1 T = 400ns (MIN) 4 t RPA Tc0 Td0 LM 5 t MRD LM 6 EMR(2) EMR(3) Te0 Tf0 LM 7 LM 8 PRE 9 tMRD tMRD tMRD tRPA tRFC tRFC tMRD MR with DLL RESET Tg0 Th0 Ti0 Tj0 REF10 REF10 LM 11 MR without DLL RESET EMR with OCD default 200 cycles of CK are required before a READ command can be issued Tk0 Tl0 Tm0 Code Code Code Code A10 = 1 Code Code Code EMR �� LM 12 t MRD LM 13 EMR with OCD exit Indicates a Break in Time Scale t MRD Valid 14 Valid Normal operation Don’t care 1Gb: x8, x16 Automotive DDR2 SDRAM Initialization
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Automotive DDR2 SDRAM MT47H128M8 -
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1Gb: x8, x16 Automotive DDR2 SDRAM
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Functional Description Automotive I
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Functional Block Diagrams The DDR2
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Ball Assignments and Descriptions F
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Table 3: FBGA 84-Ball - x16 and 60-
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Packaging Package Dimensions Figure
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FBGA Package Capacitance Table 4: I
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Table 6: Temperature Limits Paramet
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I DD7 Conditions The detailed timin
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Table 10: DDR2 I DD Specifications
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PDF: 09005aef840eff89 Micron Techno
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PDF: 09005aef840eff89 Micron Techno
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Page 39 and 40: AC and DC Operating Conditions Tabl
Page 41 and 42: Input Electrical Characteristics an
Page 43 and 44: 1Gb: x8, x16 Automotive DDR2 SDRAM
Page 45 and 46: Table 19: Output Characteristics Pa
Page 47 and 48: Figure 15: Full Strength Pull-Up Ch
Page 49 and 50: Figure 17: Reduced Strength Pull-Up
Page 51 and 52: AC Overshoot/Undershoot Specificati
Page 53 and 54: Input Slew Rate Derating 1Gb: x8, x
Page 57 and 58: Figure 23: Nominal Slew Rate for t
Page 61 and 62: Table 34: Single-Ended DQS Slew Rat
Page 63 and 64: Figure 27: Nominal Slew Rate for t
Page 65 and 66: Figure 31: AC Input Test Signal Wav
Page 67 and 68: 6. Bank addresses (BA) determine wh
Page 69 and 70: Table 38: Truth Table - Current Sta
Page 71 and 72: NO OPERATION (NOP) LOAD MODE (LM) A
Page 73 and 74: Burst Length Figure 33: MR Definiti
Page 75 and 76: Write Recovery Power-Down Mode 1Gb:
Page 77 and 78: Extended Mode Register (EMR) Figure
Page 79 and 80: On-Die Termination (ODT) ODT effect
Page 81: Extended Mode Register 2 (EMR2) Fig
Page 87 and 88: Figure 42: Multibank Activate Restr
Page 89 and 90: Figure 43: READ Latency CK# CK Comm
Page 91 and 92: Figure 45: Nonconsecutive READ Burs
Page 93 and 94: Figure 48: READ-to-PRECHARGE - BL =
Page 95 and 96: Figure 50: Bank Read - Without Auto
Page 97 and 98: Figure 52: x4, x8 Data Output Timin
Page 99 and 100: Figure 54: Data Output Timing - t A
Page 101 and 102: Figure 55: Write Burst CK# CK Comma
Page 103 and 104: Figure 58: WRITE Interrupted by WRI
Page 105 and 106: Figure 60: WRITE-to-PRECHARGE CK# C
Page 107 and 108: Figure 62: Bank Write - with Auto P
Page 109 and 110: Figure 64: Data Input Timing PRECHA
Page 111 and 112: SELF REFRESH 1Gb: x8, x16 Automotiv
Page 113 and 114: Power-Down Mode 1Gb: x8, x16 Automo
Page 115 and 116: Table 43: Truth Table - CKE 1Gb: x8
Page 117 and 118: Figure 70: WRITE-to-Power-Down or S
Page 119 and 120: Figure 74: PRECHARGE Command-to-Pow
Page 121 and 122: Reset CKE Low Anytime 1Gb: x8, x16
Page 123 and 124: ODT Timing 1Gb: x8, x16 Automotive
Page 125 and 126: MRS Command to ODT Update Delay Dur
Page 127 and 128: Figure 83: ODT Turn-On Timing When
Page 129: Figure 85: ODT Turn-On Timing When
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1Gb: x8, x16 Automotive DDR2 SDRAM - Micron

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