1Gb: x8, x16 Automotive DDR2 SDRAM - Micron

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REFRESH Figure 65: Refresh Mode CK# CK CKE The commercial temperature DDR2 SDRAM requires REFRESH cycles at an average interval of 7.8125μs (MAX) and all rows in all banks must be refreshed at least once every 64ms. The refresh period begins when the REFRESH command is registered and ends tRFC (MIN) later. The average interval must be reduced to 3.9μs (MAX) when TC exceeds 85°C. Command NOP1 NOP1 NOP1 PRE Address A10 DQS, DQS# 4 All banks One bank tCK tCH tCL REF NOP1 REF2 NOP1 NOP ACT 1 Bank Bank(s) 3 BA DQ 4 DM 4 T0 tRP 1Gb: x8, x16 Automotive DDR2 SDRAM REFRESH T1 T2 T3 T4 Ta0 Ta1 Tb0 Tb1 Tb2 tRFC (MIN) tRFC 2 Indicates a break in time scale RA RA Don’t Care Notes: 1. NOP commands are shown for ease of illustration; other valid commands may be possible at these times. CKE must be active during clock positive transitions. 2. The second REFRESH is not required and is only shown as an example of two back-toback REFRESH commands. 3. “Don’t Care” if A10 is HIGH at this point; A10 must be HIGH if more than one bank is active (must precharge all active banks). 4. DM, DQ, and DQS signals are all “Don’t Care”/High-Z for operations shown. PDF: 09005aef840eff89 1gbddr2_ait_aat.pdf – Rev. C 7/11 EN 110 Micron Technology, Inc. reserves the right to change products or specifications without notice. � 2010 Micron Technology, Inc. All rights reserved.
SELF REFRESH 1Gb: x8, x16 Automotive DDR2 SDRAM SELF REFRESH The SELF REFRESH command is initiated when CKE is LOW. The differential clock should remain stable and meet t CKE specifications at least 1 × t CK after entering self refresh mode. The procedure for exiting self refresh requires a sequence of commands. First, the differential clock must be stable and meet t CK specifications at least 1 × t CK prior to CKE going back to HIGH. Once CKE is HIGH ( t CKE [MIN] has been satisfied with three clock registrations), the DDR2 SDRAM must have NOP or DESELECT commands issued for t XSNR. A simple algorithm for meeting both refresh and DLL requirements is used to apply NOP or DESELECT commands for 200 clock cycles before applying any other command. PDF: 09005aef840eff89 1gbddr2_ait_aat.pdf – Rev. C 7/11 EN 111 Micron Technology, Inc. reserves the right to change products or specifications without notice. � 2010 Micron Technology, Inc. All rights reserved.
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Automotive DDR2 SDRAM MT47H128M8 -
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1Gb: x8, x16 Automotive DDR2 SDRAM
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Functional Description Automotive I
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Functional Block Diagrams The DDR2
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Ball Assignments and Descriptions F
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Table 3: FBGA 84-Ball - x16 and 60-
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Packaging Package Dimensions Figure
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FBGA Package Capacitance Table 4: I
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Table 6: Temperature Limits Paramet
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I DD7 Conditions The detailed timin
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Table 10: DDR2 I DD Specifications
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PDF: 09005aef840eff89 Micron Techno
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AC and DC Operating Conditions Tabl
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Input Electrical Characteristics an
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Table 19: Output Characteristics Pa
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Figure 15: Full Strength Pull-Up Ch
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Figure 17: Reduced Strength Pull-Up
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AC Overshoot/Undershoot Specificati
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Input Slew Rate Derating 1Gb: x8, x
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Figure 23: Nominal Slew Rate for t
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Page 61 and 62: Table 34: Single-Ended DQS Slew Rat
Page 63 and 64: Figure 27: Nominal Slew Rate for t
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Page 69 and 70: Table 38: Truth Table - Current Sta
Page 71 and 72: NO OPERATION (NOP) LOAD MODE (LM) A
Page 73 and 74: Burst Length Figure 33: MR Definiti
Page 75 and 76: Write Recovery Power-Down Mode 1Gb:
Page 77 and 78: Extended Mode Register (EMR) Figure
Page 79 and 80: On-Die Termination (ODT) ODT effect
Page 81 and 82: Extended Mode Register 2 (EMR2) Fig
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Page 85 and 86: 1Gb: x8, x16 Automotive DDR2 SDRAM
Page 87 and 88: Figure 42: Multibank Activate Restr
Page 89 and 90: Figure 43: READ Latency CK# CK Comm
Page 91 and 92: Figure 45: Nonconsecutive READ Burs
Page 93 and 94: Figure 48: READ-to-PRECHARGE - BL =
Page 95 and 96: Figure 50: Bank Read - Without Auto
Page 97 and 98: Figure 52: x4, x8 Data Output Timin
Page 99 and 100: Figure 54: Data Output Timing - t A
Page 101 and 102: Figure 55: Write Burst CK# CK Comma
Page 103 and 104: Figure 58: WRITE Interrupted by WRI
Page 105 and 106: Figure 60: WRITE-to-PRECHARGE CK# C
Page 107 and 108: Figure 62: Bank Write - with Auto P
Page 109: Figure 64: Data Input Timing PRECHA
Page 113 and 114: Power-Down Mode 1Gb: x8, x16 Automo
Page 115 and 116: Table 43: Truth Table - CKE 1Gb: x8
Page 117 and 118: Figure 70: WRITE-to-Power-Down or S
Page 119 and 120: Figure 74: PRECHARGE Command-to-Pow
Page 121 and 122: Reset CKE Low Anytime 1Gb: x8, x16
Page 123 and 124: ODT Timing 1Gb: x8, x16 Automotive
Page 125 and 126: MRS Command to ODT Update Delay Dur
Page 127 and 128: Figure 83: ODT Turn-On Timing When
Page 129: Figure 85: ODT Turn-On Timing When
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1Gb: x8, x16 Automotive DDR2 SDRAM - Micron

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