1. First steps in Reaktor Core - Native Instruments

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It is important to understand that turning the processing mode of an operation to integer and converting of a floating point result of the same operation to an integer is not the same. Let’s consider an example. Here we are adding two numbers 2.4 and 4.3 as floats. The result is clearly 6.7, which when converted to integer will produce 7. So the output of the following structure is 8: Now if we change the mode of the first adder to integer, instead of adding 2.4 and 4.3 we will add their rounded versions which are 2 and 4 respectively, producing 6. So the result is 7: Clock inputs completely ignore their incoming values, therefore they are normally always floats. Furthermore, signal type conversion will not be performed for the signals that are used only as clocks: Here the clock input of the Read module is still float although the module has been set to integer mode (the OBC ports look the same regardless whether they are float or integer). Integer feedback is automatically resolved in the same way as float feedback – by inserting an integer mode Z^-1 module (of course no denormal canceling is needed here). 7.3. Building an event counter Let’s build an event counter macro. The function of this macro is similar to an event accumulator, but instead of summing the values of events, this one will just count them. Integer signal type seems a logical choice for counting: 114 – REAKTOR CORE
The output and all built-in modules have been set to integer mode here. The ILatch macro is used instead of Latch for resetting the circuitry. It does exactly the same (and can be found in the same menu), buts work on integer signals. Also, an integer modulation macro is used (it’s found in Expert Macro > Modulation > Integer menu). Both inputs do not need to be set to integer mode, because they provide only clock signals. If we take a look at the structure of the event core cell containing this macro: we’ll see that the output of this module is not set to the integer mode (it’s also not possible to set it to integer mode). That’s because the core cell being a Reaktor primary level module on the outside must output a normal primarylevel event, which is a float value. Here is a testing structure for the counter module: And the resulting panel: REAKTOR CORE – 115
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REAKTOR CORE Tutorial
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Table of Contents 1. First steps in
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Appendix D. Core cell ports .......
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H.7. Audio Mix-Amp > Gain (dB) ....
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H.88. Logic > GT / IGT ............
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1. First steps in Reaktor Core 1.1.
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You may also want to save core cell
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1.3. Using core cells in a real exa
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1.4. Basic editing of core cells No
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You can shrink them back by right-c
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or design of the module. Generally,
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And here is an example of an event
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converter. As a result, our control
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The VCF section could be promising,
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There’s only one kind of module y
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As the name implies (and the info t
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Now you can type some text into the
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Instead of a nasty looking diagonal
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Some types of processing, mixing fo
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mix it with the delayed signal. Bec
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0.02ms at 44.1kHz, even less at hig
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The Latch and Bool C types of ports
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In the value field type a new value
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modules in the same way we did earl
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2.5. Using audio as control signal
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some primary-level event signals us
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is always at full amplitude. At 1 t
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The Gate2L, AND, and L2Gate modules
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Here is a picture of a continuous s
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3.3. Simultaneous events Consider t
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3.4. Processing order As you have s
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Page 69 and 70: 4.2. Object Bus Connections Object
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Page 75 and 76: 4.4. Building an event accumulator
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Page 79 and 80: Now the reset works as specified. T
Page 81 and 82: output values. Let’s try that wit
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Page 85 and 86: The name “Modulation”, although
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Page 89 and 90: 5.2. Sampling rate clock bus A coup
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Page 101 and 102: 5.6. Other bad numbers Denormal num
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Page 105 and 106: 6. Conditional processing 6.1. Even
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Page 109 and 110: First we are going to build the cir
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Page 121 and 122: And now the connection: The upper i
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Page 125 and 126: The four Write [] modules will take
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Page 131 and 132: The size property of the array can
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Page 137 and 138: Formal output precision Now that we
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Page 141 and 142: 9.3. Numerical operations Floating
Page 143 and 144: Appendix A. Reaktor Core user inter
Page 145 and 146: Appendix B. Reaktor Core concept B.
Page 147 and 148: Appendix C. Core macro ports C.1. I
Page 149 and 150: Appendix D. Core cell ports D.1. In
Page 151 and 152: F.3. Math > - Produces the differen
Page 153 and 154: F.12. Bit > Bit OR Performs the bit
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Appendix H. Standard macros H.1. Au
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H.8. Audio Mix-Amp > Invert Inverts
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H.15. Audio Mix-Amp > XFade (lin) A
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H.22. Audio Shaper > Sine Shaper 4
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H.30. Control > Ctl Pan “Pans”
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H.38. Convert > ms2sec Converts the
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to positive. The allowed RM values
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H.53. EQ > Static Filter > 1-pole s
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H.62. EQ > Static Filter > 2-pole s
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H.70. Event Processing > Ctl2Gate C
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H.79. LFO > Random LFO Generates a
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H.88. Logic > GT / IGT Compares the
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Generates 4 phase-locked audio wave
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H.105. Oscillators > Quad Osc Gener
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H.112. VCF > Diode Ladder Diode-lad
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I.4. Audio Shaper > Parabol Sat Sim
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I.10. Control > Par Ctl Shaper Appl
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I.17. EQ > HighShelf EQ 1-pole high
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I.25. EQ > Static Filter > 2-pole s
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I.33. Oscillator > 4-Wave Mst Gener
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I.39. Oscillator > MultiWave Osc Ge
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I.44. VCF > 2 Pole SV x3 S 2-pole s
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Index A Array module ..............
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1. First steps in Reaktor Core - Native Instruments

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