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1. First steps in Reaktor Core - Native Instruments

1. First steps in Reaktor Core - Native Instruments

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Note that the Read module is clocked by the <strong>in</strong>com<strong>in</strong>g event and, of course,<br />

that its OBC-connected Write module is located downstream, because we<br />

want to write after we read.<br />

The above structure works <strong>in</strong> the sense that it accumulates <strong>in</strong>com<strong>in</strong>g values<br />

and outputs their total at its output. What is miss<strong>in</strong>g is reset functionality and<br />

circuitry to ensure the correct <strong>in</strong>itial state.<br />

Let’s build the resett<strong>in</strong>g circuitry first. Because we are with<strong>in</strong> the <strong>Reaktor</strong> <strong>Core</strong><br />

world, the In <strong>in</strong>put and the Rst <strong>in</strong>put can send events simultaneously, and if<br />

we want this to be a generally usable core macro, we need to take that <strong>in</strong>to<br />

account. Let’s assume that the In and Rst <strong>in</strong>puts simultaneously produce an<br />

event. What do we want to happen? Is the reset logically supposed to happen<br />

before the accumulated event is processed or after? (This is very similar to<br />

the difference between the Latch and the Z -1 functionality, which differ only<br />

<strong>in</strong> relative process<strong>in</strong>g order for the signal and clock <strong>in</strong>puts).<br />

We suggest tak<strong>in</strong>g the Latch approach, because that module is very widely<br />

used <strong>in</strong> <strong>Reaktor</strong> <strong>Core</strong> structures, and therefore such behavior would be more<br />

<strong>in</strong>tuitive. In a Latch, the clock signal logically arrives later than the value signal.<br />

In our case, the reset signal should arrive logically after the accumulated signal<br />

(forc<strong>in</strong>g the state and the output to zero). Therefore, we need to somehow<br />

override the accumulator output with an <strong>in</strong>itial value. To achieve that we will<br />

need to use a new concept, which we are about to discuss.<br />

4.5. Event merg<strong>in</strong>g<br />

You have seen various ways of comb<strong>in</strong><strong>in</strong>g two different signals <strong>in</strong> <strong>Reaktor</strong> <strong>Core</strong>,<br />

<strong>in</strong>clud<strong>in</strong>g arithmetic operations and other ways. What has been miss<strong>in</strong>g is a<br />

way to simply merge two signals.<br />

Merg<strong>in</strong>g is not add<strong>in</strong>g. Merg<strong>in</strong>g means that the result of the operation is the last<br />

<strong>in</strong>com<strong>in</strong>g value, rather than the sum of all <strong>in</strong>com<strong>in</strong>g values. To merge signals<br />

you need to use the Merge module. Let’s take a look at how it works.<br />

Imag<strong>in</strong>e we have a Merge module with two <strong>in</strong>puts. The <strong>in</strong>itial output value<br />

(before the <strong>in</strong>itialization event) is, as for most of the modules, zero:<br />

76 – REAKTOR CORE

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