1. First steps in Reaktor Core - Native Instruments

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H.83. LFO > Sine LFO Generates a sine-shaped low-frequency control signal. The F input specifies the rate in Hz, the events at the Rst input restart the LFO at the phase specified by the event value (range 0..1). H.84. LFO > Tri LFO Generates a triangular low-frequency control signal. The F input specifies the rate in Hz, the events at the Rst input restart the LFO at the phase specified by the event value (range 0..1). H.85. Logic > AND Performs a conjunction of two logical signals (the output is 1 only if both inputs are 1). For input values other than 0 or 1 the result is undefined. H.86. Logic > Flip Flop The output is flipped between 0 and 1 each time the clock input receives an event. H.87. Logic > Gate2L Converts gate signal to logic signal. Open gate produces output value 1, closed gate produces output value 0. 186 – REAKTOR CORE
H.88. Logic > GT / IGT Compares the two incoming float/integer values and outputs 1 if the upper value is greater than the lower value, otherwise outputs 0. H.89. Logic > EQ Compares the two incoming integer values and outputs 1 if both values are equal, otherwise outputs 0. H.90. Logic > GE Compares the two incoming integer values and outputs 1 if the upper value is greater or equal to the lower value, otherwise outputs 0. H.91. Logic > L2Clock Converts a logic signal into the clock signal. Switching the input signal from 0 to 1 sends the clock event. For input values other than 0 or 1 the functionality is undefined. H.92. Logic > L2Gate Converts a logic signal to a gate signal. Switching the input signal from 0 to 1 opens the gate, switching back closes the gate. The open gate level is defined by the value at the lower input (default = 1). For input values other than 0 or 1 the functionality is undefined. REAKTOR CORE – 187
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REAKTOR CORE Tutorial
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Table of Contents 1. First steps in
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Appendix D. Core cell ports .......
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H.7. Audio Mix-Amp > Gain (dB) ....
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H.88. Logic > GT / IGT ............
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1. First steps in Reaktor Core 1.1.
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You may also want to save core cell
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1.3. Using core cells in a real exa
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1.4. Basic editing of core cells No
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You can shrink them back by right-c
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or design of the module. Generally,
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And here is an example of an event
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converter. As a result, our control
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The VCF section could be promising,
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There’s only one kind of module y
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As the name implies (and the info t
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Now you can type some text into the
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Instead of a nasty looking diagonal
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Some types of processing, mixing fo
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mix it with the delayed signal. Bec
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0.02ms at 44.1kHz, even less at hig
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The Latch and Bool C types of ports
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In the value field type a new value
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modules in the same way we did earl
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2.5. Using audio as control signal
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some primary-level event signals us
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is always at full amplitude. At 1 t
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The Gate2L, AND, and L2Gate modules
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Here is a picture of a continuous s
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3.3. Simultaneous events Consider t
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3.4. Processing order As you have s
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Event Inputs send core events to th
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Of course, in this particular case
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Now move the knob and watch the out
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4.2. Object Bus Connections Object
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As mentioned, the above structure i
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constants would send their values a
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4.4. Building an event accumulator
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� ��
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Now the reset works as specified. T
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output values. Let’s try that wit
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Should any files be found in this C
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The name “Modulation”, although
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5. Audio processing at its core 5.1
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5.2. Sampling rate clock bus A coup
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We have already seen a structure bu
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connections will be marked as inval
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As you can see, the clock input of
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left which we cannot see from the o
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samples, we have to produce several
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5.6. Other bad numbers Denormal num
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6.28319 is 2*π, which is then divi
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6. Conditional processing 6.1. Even
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In this version, the 0 output of th
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First we are going to build the cir
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default means use whatever precisio
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Switching between float and integer
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The output and all built-in modules
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The OBC chain at the bottom keeps t
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The speed of the number change in t
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And now the connection: The upper i
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This macro internally has an Index
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The four Write [] modules will take
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In general, you should also take ca
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� ��
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The size property of the array can
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So we include another macro for wra
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Page 137 and 138: Formal output precision Now that we
Page 139 and 140: 9. Building optimal structures As a
Page 141 and 142: 9.3. Numerical operations Floating
Page 143 and 144: Appendix A. Reaktor Core user inter
Page 145 and 146: Appendix B. Reaktor Core concept B.
Page 147 and 148: Appendix C. Core macro ports C.1. I
Page 149 and 150: Appendix D. Core cell ports D.1. In
Page 151 and 152: F.3. Math > - Produces the differen
Page 153 and 154: F.12. Bit > Bit OR Performs the bit
Page 155 and 156: that the module on the picture abov
Page 157 and 158: connected to the sidechain input. T
Page 159 and 160: Appendix G. Expert macros G.1. Clip
Page 161 and 162: G.12. Math > sqrt Square root appro
Page 163 and 164: G.24. Memory > Read [] Reads a valu
Page 165 and 166: Appendix H. Standard macros H.1. Au
Page 167 and 168: H.8. Audio Mix-Amp > Invert Inverts
Page 169 and 170: H.15. Audio Mix-Amp > XFade (lin) A
Page 171 and 172: H.22. Audio Shaper > Sine Shaper 4
Page 173 and 174: H.30. Control > Ctl Pan “Pans”
Page 175 and 176: H.38. Convert > ms2sec Converts the
Page 177 and 178: to positive. The allowed RM values
Page 179 and 180: H.53. EQ > Static Filter > 1-pole s
Page 181 and 182: H.62. EQ > Static Filter > 2-pole s
Page 183 and 184: H.70. Event Processing > Ctl2Gate C
Page 185: H.79. LFO > Random LFO Generates a
Page 189 and 190: Generates 4 phase-locked audio wave
Page 191 and 192: H.105. Oscillators > Quad Osc Gener
Page 193 and 194: H.112. VCF > Diode Ladder Diode-lad
Page 195 and 196: I.4. Audio Shaper > Parabol Sat Sim
Page 197 and 198: I.10. Control > Par Ctl Shaper Appl
Page 199 and 200: I.17. EQ > HighShelf EQ 1-pole high
Page 201 and 202: I.25. EQ > Static Filter > 2-pole s
Page 203 and 204: I.33. Oscillator > 4-Wave Mst Gener
Page 205 and 206: I.39. Oscillator > MultiWave Osc Ge
Page 207 and 208: I.44. VCF > 2 Pole SV x3 S 2-pole s
Page 209 and 210: Index A Array module ..............
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1. First steps in Reaktor Core - Native Instruments

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