1. First steps in Reaktor Core - Native Instruments

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9.2. Routing and merging Routing can be more or less CPU intensive depending on the situation and the platform. If you can avoid routing without adding other CPU-intensive operations to your structure, do so. Sometimes ES Ctl routing can be replaced by using Latches. If possible, do so. If you split the event path into two branches using a Router, it’s a good idea to merge the branches generated by the outputs of the Router: It’s also a good idea to merge to the incoming (unsplit) event to the Router: Merging is not necessarily done by using a Merge module. Any arithmetic or a similar module will do the job: Merging can also happen inside a macro (depending on its internal structure): It may be reasonable or necessary to merge the branches generated by different Routers, but beware of higher CPU loads in that case. 140 – REAKTOR CORE
9.3. Numerical operations Floating point addition, multiplication, subtraction, absolute value, and negation are generally the least CPU-intensive float operations. Integer addition, subtraction and negation are the least CPU-intensive integer operations. Integer absolute value is also more or less OK. DN Cancel currently uses plain addition, as you may remember. Float division, and integer multiplication and division are significantly more CPU intensive on average. It is advisable to group your operations in a way that the most CPU intensive ones get evaluated as rarely as possible. For example, if you need to compute normalized frequency by dividing the frequency in Hz by the sampling rate it could be reasonable to compute the reciprocal of the sampling rate first and multiply the frequency by the result: In the above structure, the division will be performed only when the sample rate changes, which should be pretty rare. Changes to the frequency will trigger only multiplication. Compare that to the more straightforward implementation of the same formula: where the division would be executed in response to every change of frequency. 9.4. Conversions between floats and integers Generally, avoid all unnecessary conversions between float and integer numbers. Depending on the platform such conversions could use significant amounts of CPU. The conversions that are necessary to do are OK, of course. Although the following structure might work as expected, in fact, there are two unnecessary conversions between integer and float types: REAKTOR CORE – 141
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REAKTOR CORE Tutorial
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Table of Contents 1. First steps in
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Appendix D. Core cell ports .......
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H.7. Audio Mix-Amp > Gain (dB) ....
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H.88. Logic > GT / IGT ............
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1. First steps in Reaktor Core 1.1.
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You may also want to save core cell
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1.3. Using core cells in a real exa
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1.4. Basic editing of core cells No
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You can shrink them back by right-c
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or design of the module. Generally,
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And here is an example of an event
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converter. As a result, our control
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The VCF section could be promising,
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There’s only one kind of module y
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As the name implies (and the info t
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Now you can type some text into the
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Instead of a nasty looking diagonal
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Some types of processing, mixing fo
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mix it with the delayed signal. Bec
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0.02ms at 44.1kHz, even less at hig
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The Latch and Bool C types of ports
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In the value field type a new value
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modules in the same way we did earl
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2.5. Using audio as control signal
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some primary-level event signals us
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is always at full amplitude. At 1 t
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The Gate2L, AND, and L2Gate modules
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Here is a picture of a continuous s
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3.3. Simultaneous events Consider t
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3.4. Processing order As you have s
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Event Inputs send core events to th
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Of course, in this particular case
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Now move the knob and watch the out
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4.2. Object Bus Connections Object
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As mentioned, the above structure i
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constants would send their values a
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4.4. Building an event accumulator
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� ��
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Now the reset works as specified. T
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output values. Let’s try that wit
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Should any files be found in this C
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The name “Modulation”, although
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5. Audio processing at its core 5.1
Page 89 and 90: 5.2. Sampling rate clock bus A coup
Page 91 and 92: We have already seen a structure bu
Page 93 and 94: connections will be marked as inval
Page 95 and 96: As you can see, the clock input of
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Page 101 and 102: 5.6. Other bad numbers Denormal num
Page 103 and 104: 6.28319 is 2*π, which is then divi
Page 105 and 106: 6. Conditional processing 6.1. Even
Page 107 and 108: In this version, the 0 output of th
Page 109 and 110: First we are going to build the cir
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Page 113 and 114: Switching between float and integer
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Page 117 and 118: The OBC chain at the bottom keeps t
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Page 121 and 122: And now the connection: The upper i
Page 123 and 124: This macro internally has an Index
Page 125 and 126: The four Write [] modules will take
Page 127 and 128: In general, you should also take ca
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Page 131 and 132: The size property of the array can
Page 133 and 134: So we include another macro for wra
Page 135 and 136: A new dialog will appear: What you
Page 137 and 138: Formal output precision Now that we
Page 139: 9. Building optimal structures As a
Page 143 and 144: Appendix A. Reaktor Core user inter
Page 145 and 146: Appendix B. Reaktor Core concept B.
Page 147 and 148: Appendix C. Core macro ports C.1. I
Page 149 and 150: Appendix D. Core cell ports D.1. In
Page 151 and 152: F.3. Math > - Produces the differen
Page 153 and 154: F.12. Bit > Bit OR Performs the bit
Page 155 and 156: that the module on the picture abov
Page 157 and 158: connected to the sidechain input. T
Page 159 and 160: Appendix G. Expert macros G.1. Clip
Page 161 and 162: G.12. Math > sqrt Square root appro
Page 163 and 164: G.24. Memory > Read [] Reads a valu
Page 165 and 166: Appendix H. Standard macros H.1. Au
Page 167 and 168: H.8. Audio Mix-Amp > Invert Inverts
Page 169 and 170: H.15. Audio Mix-Amp > XFade (lin) A
Page 171 and 172: H.22. Audio Shaper > Sine Shaper 4
Page 173 and 174: H.30. Control > Ctl Pan “Pans”
Page 175 and 176: H.38. Convert > ms2sec Converts the
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Page 179 and 180: H.53. EQ > Static Filter > 1-pole s
Page 181 and 182: H.62. EQ > Static Filter > 2-pole s
Page 183 and 184: H.70. Event Processing > Ctl2Gate C
Page 185 and 186: H.79. LFO > Random LFO Generates a
Page 187 and 188: H.88. Logic > GT / IGT Compares the
Page 189 and 190: Generates 4 phase-locked audio wave
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H.105. Oscillators > Quad Osc Gener
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H.112. VCF > Diode Ladder Diode-lad
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I.4. Audio Shaper > Parabol Sat Sim
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I.10. Control > Par Ctl Shaper Appl
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I.17. EQ > HighShelf EQ 1-pole high
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I.25. EQ > Static Filter > 2-pole s
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I.33. Oscillator > 4-Wave Mst Gener
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I.39. Oscillator > MultiWave Osc Ge
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I.44. VCF > 2 Pole SV x3 S 2-pole s
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Index A Array module ..............
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1. First steps in Reaktor Core - Native Instruments

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