1. First steps in Reaktor Core - Native Instruments

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A typical situation in which denormal numbers appear for prolonged periods of time is in calculating exponentially decaying values, as in filters, some envelopes, and feedback structures. In such structures, after the input signal reaches zero level, the output signal asymptotically decays to zero. Asymptotically means that the signal gets closer and closer to zero without ever reaching it. In that situation, denormal numbers can appear and stay in the structure for relatively long time (until their absolute value falls below 10 -45 ), and that can cause a significant increase in CPU load. Another situation in which denormal numbers may occur is when you change the precision of a floating point value from a higher precision (64 bit) to a lower precision (32 bit), because a value 10 -41 is not a denormal in a 64 bit precision float but it is a denormal in a 32 bit precision float (changing the precision of floats is discussed later). Let’s consider modeling an analog 1-pole lowpass filter with its cutoff set to 20 Hz. Our digital signal values will correspond to analog voltages (measured in volts). Let’s imagine that the input signal level was equal to 1V (volt) over a long enough period of time. Then the voltage at the filter output is also equal to 1V. Now we abruptly change the input voltage to zero. The output voltage will decay according to the law: V out � V e 98 – REAKTOR CORE 0 �2� f t c where f c is the filter cutoff in Hz, t is time in seconds and 0 1V � V (initial voltage). Then the output voltage will change as follows: after 0.5 sec V ≈10 out -29 volt after 0.6 sec V ≈10 out -33 volt after 0.7 sec V ≈10 out -38 volt after 0.8 sec V ≈10 out -44 volt Oops, the numbers between 10 -38 and 10 -45 are in the denormal range. So in the time period from approximately 0.7 to 0.8 seconds, our voltage is represented by a denormal value. And it’s not only inside the filter. The filter output is probably further processed by the downstream structure, causing at least the few following modules also to deal with denormal values. At a sampling rate of 44.1 kHz, the time interval of 0.1 second corresponds to 4,410 samples. Assuming that the typical ASIO buffer size is a few hundred
samples, we have to produce several buffers at a significantly higher CPU load. Should the CPU load (per buffer computation) get close enough to or exceed 100%, it will cause audio dropouts. From the above text you need to draw one conclusion: denormal values are bad in real-time audio. Reaktor primary-level modules are programmed in a way that generally prevents denormals from occurring inside them. Specifically, the DSP algorithms have been modified in a way that they generally shouldn’t produce any denormal values. If you are designing your own low-level DSP structures in Reaktor Core you also have to take care of denormals. To help you with that job we have introduced the Denormal Cancel module, available in Built-In Module > Math submenu: The Denormal Cancel module has one input and one output, and it tries to slightly modify the incoming value in a way that prevents denormals from occurring at the output: The way this module modifies the signal is not fixed and may change from one software version to another, or even from one place in the structure to another. Currently it adds a very small constant to the input value. Because of precision losses, this addition does not modify values that are large enough (a value as large as 10 -10 will not be modified at all), and because of the same precision losses, it is very unlikely that the result of addition can be a denormal value (in most of the cases it is probably even impossible). REAKTOR CORE – 99
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REAKTOR CORE Tutorial
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Table of Contents 1. First steps in
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Appendix D. Core cell ports .......
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H.7. Audio Mix-Amp > Gain (dB) ....
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H.88. Logic > GT / IGT ............
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1. First steps in Reaktor Core 1.1.
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You may also want to save core cell
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1.3. Using core cells in a real exa
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1.4. Basic editing of core cells No
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You can shrink them back by right-c
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or design of the module. Generally,
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And here is an example of an event
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converter. As a result, our control
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The VCF section could be promising,
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There’s only one kind of module y
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As the name implies (and the info t
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Now you can type some text into the
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Instead of a nasty looking diagonal
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Some types of processing, mixing fo
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mix it with the delayed signal. Bec
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0.02ms at 44.1kHz, even less at hig
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The Latch and Bool C types of ports
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In the value field type a new value
Page 47 and 48: modules in the same way we did earl
Page 49 and 50: 2.5. Using audio as control signal
Page 51 and 52: some primary-level event signals us
Page 53 and 54: is always at full amplitude. At 1 t
Page 55 and 56: The Gate2L, AND, and L2Gate modules
Page 57 and 58: Here is a picture of a continuous s
Page 59 and 60: 3.3. Simultaneous events Consider t
Page 61 and 62: 3.4. Processing order As you have s
Page 63 and 64: Event Inputs send core events to th
Page 65 and 66: Of course, in this particular case
Page 67 and 68: Now move the knob and watch the out
Page 69 and 70: 4.2. Object Bus Connections Object
Page 71 and 72: As mentioned, the above structure i
Page 73 and 74: constants would send their values a
Page 75 and 76: 4.4. Building an event accumulator
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Page 79 and 80: Now the reset works as specified. T
Page 81 and 82: output values. Let’s try that wit
Page 83 and 84: Should any files be found in this C
Page 85 and 86: The name “Modulation”, although
Page 87 and 88: 5. Audio processing at its core 5.1
Page 89 and 90: 5.2. Sampling rate clock bus A coup
Page 91 and 92: We have already seen a structure bu
Page 93 and 94: connections will be marked as inval
Page 95 and 96: As you can see, the clock input of
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Page 101 and 102: 5.6. Other bad numbers Denormal num
Page 103 and 104: 6.28319 is 2*π, which is then divi
Page 105 and 106: 6. Conditional processing 6.1. Even
Page 107 and 108: In this version, the 0 output of th
Page 109 and 110: First we are going to build the cir
Page 111 and 112: default means use whatever precisio
Page 113 and 114: Switching between float and integer
Page 115 and 116: The output and all built-in modules
Page 117 and 118: The OBC chain at the bottom keeps t
Page 119 and 120: The speed of the number change in t
Page 121 and 122: And now the connection: The upper i
Page 123 and 124: This macro internally has an Index
Page 125 and 126: The four Write [] modules will take
Page 127 and 128: In general, you should also take ca
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Page 131 and 132: The size property of the array can
Page 133 and 134: So we include another macro for wra
Page 135 and 136: A new dialog will appear: What you
Page 137 and 138: Formal output precision Now that we
Page 139 and 140: 9. Building optimal structures As a
Page 141 and 142: 9.3. Numerical operations Floating
Page 143 and 144: Appendix A. Reaktor Core user inter
Page 145 and 146: Appendix B. Reaktor Core concept B.
Page 147 and 148: Appendix C. Core macro ports C.1. I
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Appendix D. Core cell ports D.1. In
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F.3. Math > - Produces the differen
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F.12. Bit > Bit OR Performs the bit
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that the module on the picture abov
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connected to the sidechain input. T
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Appendix G. Expert macros G.1. Clip
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G.12. Math > sqrt Square root appro
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G.24. Memory > Read [] Reads a valu
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Appendix H. Standard macros H.1. Au
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H.8. Audio Mix-Amp > Invert Inverts
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H.15. Audio Mix-Amp > XFade (lin) A
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H.22. Audio Shaper > Sine Shaper 4
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H.30. Control > Ctl Pan “Pans”
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H.38. Convert > ms2sec Converts the
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to positive. The allowed RM values
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H.53. EQ > Static Filter > 1-pole s
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H.62. EQ > Static Filter > 2-pole s
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H.70. Event Processing > Ctl2Gate C
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H.79. LFO > Random LFO Generates a
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H.88. Logic > GT / IGT Compares the
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Generates 4 phase-locked audio wave
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H.105. Oscillators > Quad Osc Gener
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H.112. VCF > Diode Ladder Diode-lad
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I.4. Audio Shaper > Parabol Sat Sim
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I.10. Control > Par Ctl Shaper Appl
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I.17. EQ > HighShelf EQ 1-pole high
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I.25. EQ > Static Filter > 2-pole s
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I.33. Oscillator > 4-Wave Mst Gener
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I.39. Oscillator > MultiWave Osc Ge
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I.44. VCF > 2 Pole SV x3 S 2-pole s
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Index A Array module ..............
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1. First steps in Reaktor Core - Native Instruments

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