1. First steps in Reaktor Core - Native Instruments

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8.2. Building an audio signal selector Now let’s return to building the audio signal selector module: Here is an empty internal structure for this module: We are going to use an array of 4 float elements for storing our audio signals: Here are the properties of the array module: To write the input values into the array we will use the standard macro Write [] (Expert Macro > Memory > Write []): 122 – REAKTOR CORE
This macro internally has an Index module and a Write module, performing writing into the array element with a specified index: The upper input, of course, receives the value to be written. The [] input receives the index at which the write operation should take place. The M input receives the OBC connection to a default precision float array, and the S output is a thru connection, similar to other OBC modules like Read and Write. The M input and the S output are another type of macro port, which differs from the ones we have been using up to now. These ports can be inserted by selecting the Latch entry from the port insertion menu (the third type is the BoolCtl macro port type): Latch ports can be used for latch OBC connections (between Reads and Writes) as well as for array OBC connections. How they are used is controlled in the port’s properties: REAKTOR CORE – 123
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REAKTOR CORE Tutorial
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Table of Contents 1. First steps in
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Appendix D. Core cell ports .......
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H.7. Audio Mix-Amp > Gain (dB) ....
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H.88. Logic > GT / IGT ............
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1. First steps in Reaktor Core 1.1.
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You may also want to save core cell
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1.3. Using core cells in a real exa
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1.4. Basic editing of core cells No
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You can shrink them back by right-c
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or design of the module. Generally,
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And here is an example of an event
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converter. As a result, our control
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The VCF section could be promising,
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There’s only one kind of module y
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As the name implies (and the info t
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Now you can type some text into the
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Instead of a nasty looking diagonal
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Some types of processing, mixing fo
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mix it with the delayed signal. Bec
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0.02ms at 44.1kHz, even less at hig
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The Latch and Bool C types of ports
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In the value field type a new value
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modules in the same way we did earl
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2.5. Using audio as control signal
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some primary-level event signals us
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is always at full amplitude. At 1 t
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The Gate2L, AND, and L2Gate modules
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Here is a picture of a continuous s
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3.3. Simultaneous events Consider t
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3.4. Processing order As you have s
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Event Inputs send core events to th
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Of course, in this particular case
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Now move the knob and watch the out
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4.2. Object Bus Connections Object
Page 71 and 72: As mentioned, the above structure i
Page 73 and 74: constants would send their values a
Page 75 and 76: 4.4. Building an event accumulator
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Page 79 and 80: Now the reset works as specified. T
Page 81 and 82: output values. Let’s try that wit
Page 83 and 84: Should any files be found in this C
Page 85 and 86: The name “Modulation”, although
Page 87 and 88: 5. Audio processing at its core 5.1
Page 89 and 90: 5.2. Sampling rate clock bus A coup
Page 91 and 92: We have already seen a structure bu
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Page 95 and 96: As you can see, the clock input of
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Page 101 and 102: 5.6. Other bad numbers Denormal num
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Page 105 and 106: 6. Conditional processing 6.1. Even
Page 107 and 108: In this version, the 0 output of th
Page 109 and 110: First we are going to build the cir
Page 111 and 112: default means use whatever precisio
Page 113 and 114: Switching between float and integer
Page 115 and 116: The output and all built-in modules
Page 117 and 118: The OBC chain at the bottom keeps t
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Page 121: And now the connection: The upper i
Page 125 and 126: The four Write [] modules will take
Page 127 and 128: In general, you should also take ca
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Page 131 and 132: The size property of the array can
Page 133 and 134: So we include another macro for wra
Page 135 and 136: A new dialog will appear: What you
Page 137 and 138: Formal output precision Now that we
Page 139 and 140: 9. Building optimal structures As a
Page 141 and 142: 9.3. Numerical operations Floating
Page 143 and 144: Appendix A. Reaktor Core user inter
Page 145 and 146: Appendix B. Reaktor Core concept B.
Page 147 and 148: Appendix C. Core macro ports C.1. I
Page 149 and 150: Appendix D. Core cell ports D.1. In
Page 151 and 152: F.3. Math > - Produces the differen
Page 153 and 154: F.12. Bit > Bit OR Performs the bit
Page 155 and 156: that the module on the picture abov
Page 157 and 158: connected to the sidechain input. T
Page 159 and 160: Appendix G. Expert macros G.1. Clip
Page 161 and 162: G.12. Math > sqrt Square root appro
Page 163 and 164: G.24. Memory > Read [] Reads a valu
Page 165 and 166: Appendix H. Standard macros H.1. Au
Page 167 and 168: H.8. Audio Mix-Amp > Invert Inverts
Page 169 and 170: H.15. Audio Mix-Amp > XFade (lin) A
Page 171 and 172: H.22. Audio Shaper > Sine Shaper 4
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H.30. Control > Ctl Pan “Pans”
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H.38. Convert > ms2sec Converts the
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to positive. The allowed RM values
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H.53. EQ > Static Filter > 1-pole s
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H.62. EQ > Static Filter > 2-pole s
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H.70. Event Processing > Ctl2Gate C
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H.79. LFO > Random LFO Generates a
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H.88. Logic > GT / IGT Compares the
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Generates 4 phase-locked audio wave
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H.105. Oscillators > Quad Osc Gener
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H.112. VCF > Diode Ladder Diode-lad
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I.4. Audio Shaper > Parabol Sat Sim
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I.10. Control > Par Ctl Shaper Appl
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I.17. EQ > HighShelf EQ 1-pole high
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I.25. EQ > Static Filter > 2-pole s
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I.33. Oscillator > 4-Wave Mst Gener
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I.39. Oscillator > MultiWave Osc Ge
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I.44. VCF > 2 Pole SV x3 S 2-pole s
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Index A Array module ..............
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