VHDL Kompakt - CES

A.7 std logic 1164
Benutzung
library ieee;
use ieee.std_logic_1164.all;
Deklarationen
type std_ulogic is (’U’, ’X’, ’0’, ’1’, ’Z’, ’W’, ’L’, ’H’, ’-’);
type std_ulogic_vector is array (natural range ) of std_ulogic;
type std_logic_vector is array (natural range ) of std_logic;
subtype std_logic is resolved std_ulogic;
subtype x01 is resolved std_ulogic range ’X’ to ’1’;
subtype x01z is resolved std_ulogic range ’X’ to ’Z’;
subtype ux01 is resolved std_ulogic range ’U’ to ’1’;
subtype ux01z is resolved std_ulogic range ’U’ to ’Z’;
to_bit (〈std_ulogic〉 [, 〈xMap〉 ]) : bit
to_bitvector (〈std_(u)logic_vector〉 [, 〈xMap〉 ]) : bit_vector
to_stdulogic (〈bit〉) : std_ulogic
to_stdlogicvector (〈bit_vector〉 | 〈std_ulogic_vector〉) : std_logic_vector
to_stdulogicvector(〈bit_vector〉 | 〈std_logic_vector〉) : std_ulogic_vector
to_x01 (〈std_(u)logic〉 | 〈std_(u)logic_vector〉) : x01
(〈bit〉 | 〈bit_vector〉) : x01
to_x01z (〈std_(u)logic〉 | 〈std_(u)logic_vector〉) : x01z
(〈bit〉 | 〈bit_vector〉) : x01z
to_ux01 (〈std_(u)logic〉 | 〈std_(u)logic_vector〉) : ux01
(〈bit〉 | 〈bit_vector〉) : ux01
is_x (〈std_(u)logic〉 | 〈std_(u)logic_vector〉) : boolean
rising_edge (〈std_(u)logic〉) : boolean
falling_edge(〈std_(u)logic〉) : boolean
A.7 std logic 1164
Operatoren
Typ-a Typ-b Typ- 〈op〉
and or nand std_( u) logic | = a = a
nor xor xnor std_( u) logic_vector
not –”– = a
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