VHDL Kompakt - CES

A. Syntaxbeschreibung
A.12 reservierte Bezeichner
VHDL’93
abs else label package then
access elsif library port to
after end linkage postponed transport
alias entity literal procedure type
all exit loop process
and pure unaffected
architecture file map units
array for mod range until
assert function record use
attribute nand register
generate new reject variable
begin generic next rem
block group nor report wait
body guarded not return when
buffer null rol while
bus if ror with
impure of
case in on select xnor
component inertial open severity xor
configuration inout or shared
constant is others signal
out sla
disconnect sll
downto sra
srl
subtype
114