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document title / titre du document TRP W ORK PLAN ... - emits - ESA

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<strong>TRP</strong> Work Plan 2005-2007<br />

Description of Activities<br />

TEC-SB/7935/dc<br />

12/Feb/09<br />

<strong>TRP</strong> Reference:<br />

Title:<br />

T501-10ET<br />

High throughput highly re-configurable bent-pipe processor for access networks<br />

The proposed activity aims at the design, implementation and validation of the Proof of Concept (PoC) of a high throughput<br />

highly re-configurable and scalable digital processor for future bent-pipe satellite broadband access networks that meets these<br />

new challenging requirements in terms of flexibility and processed bandwidth (expected to be up to 50 GHz). The prototype<br />

shall demonstrate all the key functionalities of the processor (e.g. high bandwidth signal processing algorithms, channel to<br />

beam allocation flexibility, wideband digital beam forming, etc.) and assess in detail the use of cutting-edge digital<br />

technologies (e.g. 0.13 micro-m, new low power consumption ADC/DAC) needed for achieving efficient processing of the<br />

large bandwidths involved within the next generation of communication systems. For budgetary reasons the PoC will make<br />

extensive use of FPGA technology. The prototype shall be implemented at a laboratory breadboard level and is expected to<br />

work at re<strong>du</strong>ced scale in terms of processed bandwidth per beam and be scaled-down in terms implemented links. The PoC<br />

shall allow a thoroughly validation of the proposed architecture, signal processing algorithms and achievement of the<br />

performance requirements. Power and mass estimate for the final target technology shall be however performed. A real-time<br />

air interface simulator shall be developed for both up and downlink in order to provide the processor with the required IF and<br />

control signals. The simulator shall cover functions such as interference and propagation effects, satellite delays, network<br />

synchronization mechanisms, payload impairments, packet demo<strong>du</strong>lation, background signalling loading of the switch<br />

controller, etc.<br />

Deliverables:<br />

Processor Detailed Design Report PoC of a scaled-down version of the High Throughput Transparent Processor.<br />

Current TRL: TRL1 Target TRL: TRL3 Application Need/Date: TRL5 by 2009<br />

Application/Mission: Telecom Contract Duration: 18 months<br />

SW Clause : - Dossier0 Ref.: T-7931<br />

Consistency with Harmonisation<br />

Roadmap and Conclusions:<br />

<strong>TRP</strong> Reference: T501-11EE<br />

Title:<br />

New concepts for <strong>du</strong>al-gridded reflectors (study)<br />

Dual-gridded reflector antennas allow the combination of two apertures in almost the same room that would be occupied by<br />

only one normal reflector. This is achieved by using polarisation sensitive grids printed on the reflector surfaces. This concept<br />

is extremely important <strong>du</strong>e to the accommodation constraints of the platforms and lead to very high polarisation purity.<br />

Ku-band <strong>du</strong>al-gridded reflectors are widely used today on commercial satellites. This activity deals with the study of possible<br />

technological implementations of <strong>du</strong>al-gridded reflectors for telecommunications applications in Ka-band. New concept and<br />

materials are mandatory <strong>du</strong>e to high transmission losses of the front shell (approximately 0.8 dB) when Ku-band technology is<br />

considered for Ka-band. It is proposed to follow this preliminary design activity by an ARTES-funded demonstration phase.<br />

Deliverables:<br />

Design of <strong>du</strong>al-gridded reflector antenna at Ka-band. RF and mechanical samples to be used as proof of concept.<br />

Current TRL: TRL1 Target TRL: TRL3 Application Need/Date: TRL5 by 2009<br />

Application/Mission: Satellite Telecommunication systems Contract Duration: 18 months<br />

SW Clause : - Dossier0 Ref.: T-7832<br />

Consistency with Harmonisation<br />

Roadmap and Conclusions:<br />

Page 106 of 227

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