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TRP Work Plan 2005-2007
Description of Activities
TEC-SB/7935/dc
12/Feb/09
TRP Reference:
Title:
T608-42ET
Deep-Sub-Micron ASIC technology assessment and High-Speed-Serial-Links design
The present activty is in line with the DSM (Deep Submicron Microelectronics) initiative strategy paper (ESA/IPC(2006)88).
The activity aims at assessing deep submicron (i.e. 90 nm or below) Application-Specific-Integrated-Circuits (ASIC)
technology with higher density chips and lower power consumption for on-board processing applications. Together with the
ASICs’ core processing capabilities it is mandatory to improve the efficiency of data transportation (between ASICs, boards
and equipments) by mean of embedded High-Speed-Serial-Link (HSSL). The design of ~10Gbps HSSLs with the selected
ASIC process is a contextual objective of this activity.
The activity shall encompass feasibility study, assessment and trade-offs of the following key issues:
- Processes trade offs and selection.
- Radiation evaluation (complementary tests): 1. Heavy ions, heavy protons and total dose effects; 2. SEE and SET
characterisation; 3. Displacement damage; 4. Radiations effects on high k dielectric.
- Reliability: 1. Electro migration; 2. Life time.
- Proposal for hardening techniques in order to cope with radiation and reliability issues: 1. Enhancement at process level; 2.
Enhancement at layout and cells design level; 3. Identification of the library cells requiring a redesign; 4. Identification of the
work involved in order to harden the selected cells or eventually design new ones (clock tree buffers …); 5. Assessment CAD
tool flow to support rad-hard library (hardened clock-tree network, TMR, etc.).
- High speed serial links: 1. Assessment of the selected process to offer embedded high speed serial links able to provide a
10 Gbps data rate while minimising power consumption (300mW per transceiver) and area; 2. Performance and architecture
trade offs; 3. Design of the transceiver IP and implementation of the hardening techniques studied previously; 4. Layout; 5.
Simulation post layout.
- Preliminary study to define packaging options.
- Sustainability of the space business (manufacturing costs, process lifetime, etc.): 1. The manufacturer shall propose a
business model for future development activities and identify NRE and RE costs; 2. The manufacturer shall propose a
sustainable model related to space business and guaranty access and support to the technology at fair conditions.
Deliverables:
Radiation and reliability reports, design rule recommendations, preliminary design and simulation report on HSSL, roadmap
for the packaging technology, business model definition.
Current TRL: TRL2-3 Target TRL: TRL3-4 Application Need/Date: TRL5/6 >2011
TLC: on-board processing, SCI: science
& remote sensing instruments, EO:
Application/Mission:
instruments, TLM&control, high-speed
Contract Duration: 18 months
rate data downlink.
SW Clause : - Dossier0 Ref.: T-7742
Consistency with Harmonisation
Roadmap and Conclusions:
ESA/IPC(2006)88
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