DE2-115: User Manual
DE2-115: User Manual
DE2-115: User Manual
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Figure 4-14 LVDS interface on HSMC connector and Cyclone IV E FPGA<br />
Signal Name<br />
HSMC_CLKIN0<br />
HSMC_CLKIN_N1<br />
HSMC_CLKIN_N2<br />
HSMC_CLKIN_P1<br />
HSMC_CLKIN_P2<br />
HSMC_CLKOUT0<br />
Table 4-9<br />
FPGA Pin<br />
No.<br />
PIN_AH15<br />
PIN_J28<br />
PIN_Y28<br />
PIN_J27<br />
PIN_Y27<br />
PIN_AD28<br />
HSMC_CLKOUT_N1 PIN_G24<br />
HSMC_CLKOUT_N2 PIN_V24<br />
HSMC_CLKOUT_P1 PIN_G23<br />
Pin Assignments for HSMC connector<br />
Description<br />
Dedicated clock input<br />
LVDS RX or CMOS I/O or differential clock input<br />
LVDS RX or CMOS I/O or differential clock input<br />
LVDS RX or CMOS I/O or differential clock input<br />
LVDS RX or CMOS I/O or differential clock input<br />
42<br />
I/O Standard<br />
Depending<br />
on JP6<br />
Depending<br />
on JP7<br />
Depending<br />
on JP7<br />
Depending<br />
on JP7<br />
Depending<br />
on JP7<br />
Depending<br />
Dedicated clock output<br />
on JP7<br />
LVDS TX or CMOS I/O or differential clock input/output Depending<br />
on JP7<br />
LVDS TX or CMOS I/O or differential clock input/output Depending<br />
on JP7<br />
LVDS TX or CMOS I/O or differential clock input/output Depending<br />
on JP7<br />
HSMC_CLKOUT_P2 PIN_V23<br />
LVDS TX or CMOS I/O or differential clock input/output Depending<br />
on JP7<br />
HSMC_D[0] PIN_AE26 LVDS TX or CMOS I/O Depending<br />
on JP7<br />
HSMC_D[1] PIN_AE28 LVDS RX or CMOS I/O Depending<br />
on JP7<br />
HSMC_D[2] PIN_AE27 LVDS TX or CMOS I/O Depending<br />
on JP7<br />
HSMC_D[3] PIN_AF27 LVDS RX or CMOS I/O Depending<br />
on JP7<br />
HSMC_RX_D_N[0] PIN_F25 LVDS RX bit 0n or CMOS I/O Depending