DE2-115: User Manual
DE2-115: User Manual
DE2-115: User Manual
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Figure 4-23 Connections between FPGA and Audio CODEC<br />
Table 4-17<br />
Audio CODEC Pin Assignments<br />
Signal Name FPGA Pin No. Description I/O Standard<br />
AUD_ADCLRCK PIN_C2 Audio CODEC ADC LR Clock 3.3V<br />
AUD_ADCDAT PIN_D2 Audio CODEC ADC Data 3.3V<br />
AUD_DACLRCK PIN_E3 Audio CODEC DAC LR Clock 3.3V<br />
AUD_DACDAT PIN_D1 Audio CODEC DAC Data 3.3V<br />
AUD_XCK PIN_E1 Audio CODEC Chip Clock 3.3V<br />
AUD_BCLK PIN_F2 Audio CODEC Bit-Stream Clock 3.3V<br />
I2C_SCLK PIN_B7 I2C Clock 3.3V<br />
I2C_SDAT PIN_A8 I2C Data 3.3V<br />
Note: If the HSMC loopback adapter is mounted, the I2C_SCL will be directly routed back<br />
to I2C_SDA. Because audio chip, TV decoder chip and HSMC share one I2C bus, therefore<br />
audio and video chip won’t function correctly.<br />
4.12 RS-232 Serial Port<br />
The <strong>DE2</strong>-<strong>115</strong> board uses the ZT3232 transceiver chip and a 9-pin DB9 connector for RS-232<br />
communications. For detailed information on how to use the transceiver, please refer to the<br />
datasheet, which is available on the manufacturer‟s website, or in the <strong>DE2</strong>_<strong>115</strong>_datasheets\RS-232<br />
folder on the <strong>DE2</strong>-<strong>115</strong> System CD. Figure 4-24 shows the related schematics, and Table 4-18 lists<br />
the Cyclone IV E FPGA pin assignments.<br />
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