DE2-115: User Manual

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You will need to perform a hardware reset after any change for enabling new settings. Table 4-21 and Table 4-22 describe the working mode settings for ENET0 PHY (U8) and ENET1 PHY (U9) respectively. In addition, it is dynamically configurable to support 10Mbps, 100Mbps (Fast Ethernet) or 1000Mbps (Gigabit Ethernet) operation using standard Cat 5e UTP cabling. The associated pin assignments are listed in Table 4-23. For detailed information on how to use the 88E1111 refers to its datasheet and application notes, which are available on the manufacturer‟s website. Figure 4-27 Connections between FPGA and Ethernet Figure 4-28 Working mode setup header for Ethernet PHY Table 4-21 JP1 Jumper Settings Short Pins 1 and 2 Short Pins 2 and 3 Jumper Settings for Working Mode of ENET0 (U8) ENET0 PHY Working Mode RGMII Mode MII Mode 57
Table 4-22 JP2 Jumper Settings Short Pins 1 and 2 Short Pins 2 and 3 Jumper Settings for Working Mode of ENET1 (U9) ENET1 PHY Working Mode RGMII Mode MII Mode Table 4-23 Pin Assignments for Fast Ethernet Signal Name FPGA Pin No. Description I/O Standard ENET0_GTX_CLK PIN_A17 GMII Transmit Clock 1 2.5V ENET0_INT_N PIN_A21 Interrupt open drain output 1 2.5V ENET0_LINK100 PIN_C14 Parallel LED output of 100BASE-TX link 1 3.3V ENET0_MDC PIN_C20 Management data clock reference 1 2.5V ENET0_MDIO PIN_B21 Management data 1 2.5V ENET0_RST_N PIN_C19 Hardware reset signal 1 2.5V ENET0_RX_CLK PIN_A15 GMII and MII receive clock 1 2.5V ENET0_RX_COL PIN_E15 GMII and MII collision 1 2.5V ENET0_RX_CRS PIN_D15 GMII and MII carrier sense 1 2.5V ENET0_RX_DATA[0] PIN_C16 GMII and MII receive data[0] 1 2.5V ENET0_RX_DATA[1] PIN_D16 GMII and MII receive data[1] 1 2.5V ENET0_RX_DATA[2] PIN_D17 GMII and MII receive data[2] 1 2.5V ENET0_RX_DATA[3] PIN_C15 GMII and MII receive data[3] 1 2.5V ENET0_RX_DV PIN_C17 GMII and MII receive data valid 1 2.5V ENET0_RX_ER PIN_D18 GMII and MII receive error 1 2.5V ENET0_TX_CLK PIN_B17 MII transmit clock 1 2.5V ENET0_TX_DATA[0] PIN_C18 MII transmit data[0] 1 2.5V ENET0_TX_DATA[1] PIN_D19 MII transmit data[1] 1 2.5V ENET0_TX_DATA[2] PIN_A19 MII transmit data[2] 1 2.5V ENET0_TX_DATA[3] PIN_B19 MII transmit data[3] 1 2.5V ENET0_TX_EN PIN_A18 GMII and MII transmit enable 1 2.5V ENET0_TX_ER PIN_B18 GMII and MII transmit error 1 2.5V ENET1_GTX_CLK PIN_C23 GMII Transmit Clock 2 2.5V ENET1_INT_N PIN_D24 Interrupt open drain output 2 2.5V ENET1_LINK100 PIN_D13 Parallel LED output of 100BASE-TX link 2 3.3V ENET1_MDC PIN_D23 Management data clock reference 2 2.5V ENET1_MDIO PIN_D25 Management data 2 2.5V ENET1_RST_N PIN_D22 Hardware reset signal 2 2.5V ENET1_RX_CLK PIN_B15 GMII and MII receive clock 2 2.5V ENET1_RX_COL PIN_B22 GMII and MII collision 2 2.5V ENET1_RX_CRS PIN_D20 GMII and MII carrier sense 2 2.5V ENET1_RX_DATA[0] PIN_B23 GMII and MII receive data[0] 2 2.5V ENET1_RX_DATA[1] PIN_C21 GMII and MII receive data[1] 2 2.5V ENET1_RX_DATA[2] PIN_A23 GMII and MII receive data[2] 2 2.5V ENET1_RX_DATA[3] PIN_D21 GMII and MII receive data[3] 2 2.5V ENET1_RX_DV PIN_A22 GMII and MII receive data valid 2 2.5V ENET1_RX_ER PIN_C24 GMII and MII receive error 2 2.5V 58
Page 2 and 3:
CONTENTS Chapter 1 DE2-115 Package
Page 4 and 5:
6.9 IR Receiver Demonstration .....
Page 6 and 7:
Bag of six rubber (silicon) covers
Page 8 and 9: Chapter 2 Introduction of the Alter
Page 10 and 11: One 40-pin Expansion Header with di
Page 12 and 13: 40-pin expansion port o Configurabl
Page 14 and 15: You can also connect a microphone t
Page 16 and 17: 5. The DE2_115_ControlPanel.sof bit
Page 18 and 19: Figure 3-3 Controlling LEDs Choosin
Page 20 and 21: Figure 3-6 Monitoring switches and
Page 22 and 23: The Sequential Read function is use
Page 24 and 25: 3.7 SD Card The function is designe
Page 26 and 27: 1. Choosing the VGA tab leads to th
Page 28 and 29: Figure 3-14 Testing the IR receiver
Page 30 and 31: Chapter 4 Using the DE2-115 Board T
Page 32 and 33: • Configuring the FPGA in JTAG Mo
Page 34 and 35: Figure 4-6 Connections between the
Page 36 and 37: Table 4-1 Pin Assignments for Slide
Page 38 and 39: HEX0[5] PIN_J22 Seven Segment Digit
Page 40 and 41: 4.6 Using the LCD Module The LCD mo
Page 42 and 43: Figure 4-13 HSMC VCCIO supply volta
Page 44 and 45: HSMC_RX_D_N[1] PIN_C27 HSMC_RX_D_N[
Page 46 and 47: HSMC_TX_D_N[14] PIN_U28 HSMC_TX_D_N
Page 48 and 49: The voltage level of the I/O pins o
Page 50 and 51: Figure 4-19 Using Emulated LVDS on
Page 52 and 53: 4.10 Using VGA The DE2-115 board in
Page 54 and 55: Table 4-16 Pin Assignments for ADV7
Page 56 and 57: Figure 4-24 Connections between FPG
Page 60 and 61: ENET1_TX_CLK PIN_C22 MII transmit c
Page 62 and 63: 4.17 Using the USB Interface The DE
Page 64 and 65: Table 4-26 IR Pin Assignments Signa
Page 66 and 67: • EEPROM The board has 32Kb EEPRO
Page 68 and 69: SRAM_DQ[7] PIN_AF7 SRAM Data[7] 3.3
Page 70 and 71: FL_ADDR[15] PIN_Y10 FLASH Address[1
Page 72 and 73: The top-level design file contains
Page 74 and 75: • System Configuration Under Syst
Page 76 and 77: Figure 5-6 HSMC Expansion Group The
Page 78 and 79: Chapter 6 Examples of Advanced Demo
Page 80 and 81: Finally, the YcrCb_to_RGB block con
Page 82 and 83: mouse connected to DE2-115 board. W
Page 84 and 85: sends a different USB packet to the
Page 86 and 87: Figure 6-7 Block diagram of the Kar
Page 88 and 89: Figure 6-9 Block Diagram of the SD
Page 90 and 91: Figure 6-11 Insert SD Card for the
Page 92 and 93: Main WAVE Lib System Call SEG7 I2C
Page 94 and 95: Figure 6-15 The setup for the SD mu
Page 96 and 97: Figure 6-16 Waveforms on two lines
Page 98 and 99: Figure 6-18 Remote controller Table
Page 100 and 101: We can apply the IR receiver to man
Page 102 and 103: Figure 6-23 Block diagram of the Mu
Page 104 and 105: Figure 6-24 The Setup of the Music
Page 106 and 107: • Demonstration Setup, File Locat
Page 108 and 109:
Figure 6-27 MII interface MAC Confi
Page 110 and 111:
Figure 6-29 MAC Options Configurati
Page 112 and 113:
Figure 6-32 PHY connected to the MA
Page 114 and 115:
Ethernet 1 respectively. Table 6-9
Page 116:
Chapter 7 Appendix 7.1 Revision His
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