DE2-115: User Manual

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ENET1_TX_CLK PIN_C22 MII transmit clock 2 2.5V ENET1_TX_DATA[0] PIN_C25 MII transmit data[0] 2 2.5V ENET1_TX_DATA[1] PIN_A26 MII transmit data[1] 2 2.5V ENET1_TX_DATA[2] PIN_B26 MII transmit data[2] 2 2.5V ENET1_TX_DATA[3] PIN_C26 MII transmit data[3] 2 2.5V ENET1_TX_EN PIN_B25 GMII and MII transmit enable 2 2.5V ENET1_TX_ER PIN_A25 GMII and MII transmit error 2 2.5V ENETCLK_25 PIN_A14 Ethernet clock source 3.3V 4.15 TV Decoder The DE2-115 board is equipped with an Analog Device ADV7180 TV decoder chip. The ADV7180 is an integrated video decoder that automatically detects and converts a standard analog baseband television signals (NTSC, PAL, and SECAM) into 4:2:2 component video data compatible with the 8-bit ITU-R BT.656 interface standard. The ADV7180 is compatible with a broad range of video devices, including DVD players, tape-based sources, broadcast sources, and security/surveillance cameras. The registers in the TV decoder can be programmed by a serial I2C bus, which is connected to the Cyclone IV E FPGA as indicated in Figure 4-29. Note that the I2C address W/R of the TV decoder (U6) is 0x40/0x41. The pin assignments are listed in Table 4-24. Detailed information of the ADV7180 is available on the manufacturer‟s website, or in the DE2_115_datasheets\TV Decoder folder on the DE2-115 System CD. Figure 4-29 Connections between FPGA and TV Decoder 59
Note: If the HSMC loopback adapter is mounted, the I2C_SCL will be directly routed back to I2C_SDA. Because audio chip, TV decoder chip and HSMC share one I2C bus, therefore audio and video chip won’t function correctly. Table 4-24 TV Decoder Pin Assignments Signal Name FPGA Pin No. Description I/O Standard TD_ DATA [0] PIN_E8 TV Decoder Data[0] 3.3V TD_ DATA [1] PIN_A7 TV Decoder Data[1] 3.3V TD_ DATA [2] PIN_D8 TV Decoder Data[2] 3.3V TD_ DATA [3] PIN_C7 TV Decoder Data[3] 3.3V TD_ DATA [4] PIN_D7 TV Decoder Data[4] 3.3V TD_ DATA [5] PIN_D6 TV Decoder Data[5] 3.3V TD_ DATA [6] PIN_E7 TV Decoder Data[6] 3.3V TD_ DATA [7] PIN_F7 TV Decoder Data[7] 3.3V TD_HS PIN_E5 TV Decoder H_SYNC 3.3V TD_VS PIN_E4 TV Decoder V_SYNC 3.3V TD_CLK27 PIN_B14 TV Decoder Clock Input. 3.3V TD_RESET_N PIN_G7 TV Decoder Reset 3.3V I2C_SCLK PIN_B7 I2C Clock 3.3V I2C_SDAT PIN_A8 I2C Data 3.3V 4.16 Implementing a TV Encoder Although the DE2-115 board does not include a TV encoder chip, the ADV7123 (10-bit high-speed triple ADCs) can be used to implement a professional-quality TV encoder with the digital processing part implemented in the Cyclone IV E FPGA. Figure 4-30 shows a block diagram of a TV encoder implemented in this manner. Figure 4-30 A TV Encoder that uses the Cyclone IV E FPGA and the ADV7123 60
Page 2 and 3:
CONTENTS Chapter 1 DE2-115 Package
Page 4 and 5:
6.9 IR Receiver Demonstration .....
Page 6 and 7:
Bag of six rubber (silicon) covers
Page 8 and 9:
Chapter 2 Introduction of the Alter
Page 10 and 11: One 40-pin Expansion Header with di
Page 12 and 13: 40-pin expansion port o Configurabl
Page 14 and 15: You can also connect a microphone t
Page 16 and 17: 5. The DE2_115_ControlPanel.sof bit
Page 18 and 19: Figure 3-3 Controlling LEDs Choosin
Page 20 and 21: Figure 3-6 Monitoring switches and
Page 22 and 23: The Sequential Read function is use
Page 24 and 25: 3.7 SD Card The function is designe
Page 26 and 27: 1. Choosing the VGA tab leads to th
Page 28 and 29: Figure 3-14 Testing the IR receiver
Page 30 and 31: Chapter 4 Using the DE2-115 Board T
Page 32 and 33: • Configuring the FPGA in JTAG Mo
Page 34 and 35: Figure 4-6 Connections between the
Page 36 and 37: Table 4-1 Pin Assignments for Slide
Page 38 and 39: HEX0[5] PIN_J22 Seven Segment Digit
Page 40 and 41: 4.6 Using the LCD Module The LCD mo
Page 42 and 43: Figure 4-13 HSMC VCCIO supply volta
Page 44 and 45: HSMC_RX_D_N[1] PIN_C27 HSMC_RX_D_N[
Page 46 and 47: HSMC_TX_D_N[14] PIN_U28 HSMC_TX_D_N
Page 48 and 49: The voltage level of the I/O pins o
Page 50 and 51: Figure 4-19 Using Emulated LVDS on
Page 52 and 53: 4.10 Using VGA The DE2-115 board in
Page 54 and 55: Table 4-16 Pin Assignments for ADV7
Page 56 and 57: Figure 4-24 Connections between FPG
Page 58 and 59: You will need to perform a hardware
Page 62 and 63: 4.17 Using the USB Interface The DE
Page 64 and 65: Table 4-26 IR Pin Assignments Signa
Page 66 and 67: • EEPROM The board has 32Kb EEPRO
Page 68 and 69: SRAM_DQ[7] PIN_AF7 SRAM Data[7] 3.3
Page 70 and 71: FL_ADDR[15] PIN_Y10 FLASH Address[1
Page 72 and 73: The top-level design file contains
Page 74 and 75: • System Configuration Under Syst
Page 76 and 77: Figure 5-6 HSMC Expansion Group The
Page 78 and 79: Chapter 6 Examples of Advanced Demo
Page 80 and 81: Finally, the YcrCb_to_RGB block con
Page 82 and 83: mouse connected to DE2-115 board. W
Page 84 and 85: sends a different USB packet to the
Page 86 and 87: Figure 6-7 Block diagram of the Kar
Page 88 and 89: Figure 6-9 Block Diagram of the SD
Page 90 and 91: Figure 6-11 Insert SD Card for the
Page 92 and 93: Main WAVE Lib System Call SEG7 I2C
Page 94 and 95: Figure 6-15 The setup for the SD mu
Page 96 and 97: Figure 6-16 Waveforms on two lines
Page 98 and 99: Figure 6-18 Remote controller Table
Page 100 and 101: We can apply the IR receiver to man
Page 102 and 103: Figure 6-23 Block diagram of the Mu
Page 104 and 105: Figure 6-24 The Setup of the Music
Page 106 and 107: • Demonstration Setup, File Locat
Page 108 and 109: Figure 6-27 MII interface MAC Confi
Page 110 and 111:
Figure 6-29 MAC Options Configurati
Page 112 and 113:
Figure 6-32 PHY connected to the MA
Page 114 and 115:
Ethernet 1 respectively. Table 6-9
Page 116:
Chapter 7 Appendix 7.1 Revision His
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DE2-115: User Manual

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