Scientific and Technical Aerospace Reports Volume 38 July 28, 2000

higher-order logic, category theory, and algebraic specifications, as incorporated into the HOL theorem prover and the Specware
system for specification composition, refinement, and code synthesis. This report presents a HOL formulation of the primary
mathematical concepts underlying Specware, fully explicating the underlying principles of construction and composition. Furthermore,
the purpose of computer-assisted reasoning is to allow nonexperts in a given domain to nonetheless have confidence
in their analysis. The HOL formulation describes the relevant concepts in an executable form that nonexperts can use in the future
to construct assured specifications and ultimately assured code.
DTIC
Software Engineering; Program Verification (Computers); Computer Techniques
20000064085 California Univ., Dept. of Electrical and Computer Engineering, Davis, CA USA
Error Control Coding Techniques for Space and Satellite Communications
Lin, Shu, California Univ., USA; May 24, 2000; 30p; In English
Contract(s)/Grant(s): NAG5-9025
Report No.(s): Rept-00-001; No Copyright; Avail: CASI; A03, Hardcopy; A01, Microfiche
This paper presents a concatenated turbo coding system in which a Reed-Solomom outer code is concatenated with a binary
turbo inner code. In the proposed system, the outer code decoder and the inner turbo code decoder interact to achieve both good
bit error and frame error performances. The outer code decoder helps the inner turbo code decoder to terminate its decoding iteration
while the inner turbo code decoder provides soft-output information to the outer code decoder to carry out a reliability-based
soft-decision decoding. In the case that the outer code decoding fails, the outer code decoder instructs the inner code decoder to
continue its decoding iterations until the outer code decoding is successful or a preset maximum number of decoding iterations
is reached. This interaction between outer and inner code decoders reduces decoding delay. Also presented in the paper are an
effective criterion for stopping the iteration process of the inner code decoder and a new reliability-based decoding algorithm for
nonbinary codes.
Author
Concatenated Codes; Binary Codes; Bit Error Rate; Error Analysis; Reed-Solomon Codes; Decoding; Decoders
20000064580 NASA Ames Research Center, Moffett Field, CA USA
A Parallel Genetic Algorithm for Automated Electronic Circuit Design
Long, Jason D., NASA Ames Research Center, USA; Colombano, Silvano P., NASA Ames Research Center, USA; Haith, Gary
L., NASA Ames Research Center, USA; Stassinopoulos, Dimitris, NASA Ames Research Center, USA; Welcome to the NASA
High Performance Computing and Communications Computational Aerosciences (CAS) Workshop 2000; February 2000; In
English; See also 20000064579; No Copyright; Abstract Only; Available from CASI only as part of the entire parent document
Parallelized versions of genetic algorithms (GAs) are popular primarily for three reasons: the GA is an inherently parallel
algorithm, typical GA applications are very compute intensive, and powerful computing platforms, especially Beowulf-style computing
clusters, are becoming more affordable and easier to implement. In addition, the low communication bandwidth required
allows the use of inexpensive networking hardware such as standard office ethernet. In this paper we describe a parallel GA and
its use in automated high-level circuit design. Genetic algorithms are a type of trial-and-error search technique that are guided
by principles of Darwinian evolution. Just as the genetic material of two living organisms can intermix to produce offspring that
are better adapted to their environment, GAs expose genetic material, frequently strings of 1s and Os, to the forces of artificial
evolution: selection, mutation, recombination, etc. GAs start with a pool of randomly-generated candidate solutions which are
then tested and scored with respect to their utility. Solutions are then bred by probabilistically selecting high quality parents and
recombining their genetic representations to produce offspring solutions. Offspring are typically subjected to a small amount of
random mutation. After a pool of offspring is produced, this process iterates until a satisfactory solution is found or an iteration
limit is reached. Genetic algorithms have been applied to a wide variety of problems in many fields, including chemistry, biology,
and many engineering disciplines. There are many styles of parallelism used in implementing parallel GAs. One such method is
called the master-slave or processor farm approach. In this technique, slave nodes are used solely to compute fitness evaluations
(the most time consuming part). The master processor collects fitness scores from the nodes and performs the genetic operators
(selection, reproduction, variation, etc.). Because of dependency issues in the GA, it is possible to have idle processors. However,
as long as the load at each processing node is similar, the processors are kept busy nearly all of the time. In applying GAs to circuit
design, a suitable genetic representation ’is that of a circuit-construction program. We discuss one such circuit-construction programming
language and show how evolution can generate useful analog circuit designs. This language has the desirable property
that virtually all sets of combinations of primitives result in valid circuit graphs. Our system allows circuit size (number of
devices), circuit topology, and device values to be evolved. Using a parallel genetic algorithm and circuit simulation software,
we present experimental results as applied to three analog filter and two amplifier design tasks. For example, a figure shows an
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