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ComputerAided_Design_Engineering_amp_Manufactur.pdf

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TABLE 1.6<br />

Tolerance synthesis is defined as the process of allocating tolerances to the size, form, and location of<br />

geometric entities of a component such that the cost incurred due to tolerances is minimized while<br />

satisfying functional and assembly requirements. Tolerance synthesis is a two-step procedure that involves<br />

the following tasks: (a) mapping part functions to equivalent functional tolerance limits and (b) constraining<br />

the functional tolerance limits with respect to manufacturing, assembly, and inspection constraints.<br />

Associated with tolerance synthesis is the issue of representation of tolerances such that it could be<br />

used effectively for the tasks of tolerance analysis and other downstream manufacturing activities. In this<br />

research work, we have demonstrated the application of ICAD techniques for performing the above two<br />

© 2001 by CRC Press LLC<br />

Feature Characteristics as Obtained from the PDM of the Raw Stock and the Finished Workpiece<br />

Product Data Model—Raw Stock<br />

Number of features—10, Raw stock dimensions—210 � 90 � 12<br />

Finished workpiece dimensions—200 � 85 � 10, Raw stock hardness—200 BHN<br />

Product Data Model—Finished Workpiece<br />

Specifications Feature<br />

Feature<br />

Feature<br />

1<br />

2,3<br />

4,5,6,7,8,9,10<br />

Type Square slot Square hole Cylindrical hole<br />

Surface-id S11, S12, S13 S21, S22, S23, S24,<br />

S31, S32, S33, S34<br />

S41, S51, S61, S71, S81, S91, S101<br />

Dimensions 5, 5, 200 20, 10, 100 5, 10<br />

Location (0, 0, 0) (40, 0, 0)<br />

(5, �98,<br />

0), ( �5,<br />

�98,<br />

0), (5, 98, 0)<br />

( �40,<br />

0, 0)<br />

(5, 98, 0), (3, �58,<br />

0), (3, 38, 0)<br />

( �3,<br />

83, 0)<br />

Finish 4.0 2.0 0.005<br />

Face-attachment 2 3 2<br />

Tolerance-info Std. Tol. Std. Tol. Size: �/<br />

�0.09,<br />

⊥: 0.02<br />

FIGURE 1.11<br />

P<br />

IGES (View Independent)<br />

- -<br />

SET<br />

VDA<br />

Process planner<br />

NC code generator<br />

Project Data Manager<br />

- -<br />

Pearl Data Manager<br />

- -<br />

Families<br />

Backup<br />

Abort<br />

CAEDS Graphics<br />

CAEDS V4R2M0: Solid - Modeling<br />

A screen dump of the user interface for the process planner along with a test part created in FBDS.

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