PIC16F8X, 18-Pin FLASH/EEPROM 8-Bit MCU Data Sheet - Microchip

More documents

Recommendations

Info

PIC16F8X 4.2 Data Memory Organization The data memory is partitioned into two areas. The first is the Special Function Registers (SFR) area, while the second is the General Purpose Registers (GPR) area. The SFRs control the operation of the device. Portions of data memory are banked. This is for both the SFR area and the GPR area. The GPR area is banked to allow greater than 116 bytes of general purpose RAM. The banked areas of the SFR are for the registers that control the peripheral functions. Banking requires the use of control bits for bank selection. These control bits are located in the STATUS Register. Figure 4-1 and Figure 4-2 show the data memory map organization. Instructions MOVWF and MOVF can move values from the W register to any location in the register file (“F”), and vice-versa. The entire data memory can be accessed either directly using the absolute address of each register file or indirectly through the File Select Register (FSR) (Section 4.5). Indirect addressing uses the present value of the RP1:RP0 bits for access into the banked areas of data memory. Data memory is partitioned into two banks which contain the general purpose registers and the special function registers. Bank 0 is selected by clearing the RP0 bit (STATUS). Setting the RP0 bit selects Bank 1. Each Bank extends up to 7Fh (128 bytes). The first twelve locations of each Bank are reserved for the Special Function Registers. The remainder are General Purpose Registers implemented as static RAM. 4.2.1 GENERAL PURPOSE REGISTER FILE All devices have some amount of General Purpose Register (GPR) area. Each GPR is 8 bits wide and is accessed either directly or indirectly through the FSR (Section 4.5). The GPR addresses in bank 1 are mapped to addresses in bank 0. As an example, addressing location 0Ch or 8Ch will access the same GPR. 4.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers (Figure 4-1, Figure 4-2 and Table 4-1) are used by the CPU and Peripheral functions to control the device operation. These registers are static RAM. The special function registers can be classified into two sets, core and peripheral. Those associated with the core functions are described in this section. Those related to the operation of the peripheral features are described in the section for that specific feature. DS30430C-page 12 © 1998 Microchip Technology Inc.
FIGURE 4-1: REGISTER FILE MAP - PIC16F83/CR83 File Address 00h Indirect addr. 80h 01h 81h 02h 82h (1) Indirect addr. (1) File Address TMR0 OPTION PCL PCL 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 2Fh 30h STATUS FSR PORTA PORTB EEDATA EEADR PCLATH INTCON 36 General Purpose registers (SRAM) STATUS FSR TRISA TRISB EECON1 EECON2 (1) PCLATH INTCON Mapped (accesses) in Bank 0 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch AFh B0h 7Fh FFh Bank 0 Bank 1 Unimplemented data memory location; read as ’0’. Note 1: Not a physical register. PIC16F8X FIGURE 4-2: REGISTER FILE MAP - PIC16F84/CR84 File Address 00h Indirect addr. 80h 01h 81h 02h 82h (1) Indirect addr. (1) File Address TMR0 OPTION PCL PCL © 1998 Microchip Technology Inc. DS30430C-page 13 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 4Fh 50h STATUS FSR PORTA PORTB EEDATA EEADR PCLATH INTCON 68 General Purpose registers (SRAM) STATUS FSR TRISA TRISB EECON1 EECON2 (1) PCLATH INTCON Mapped (accesses) in Bank 0 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 7Fh FFh Bank 0 Bank 1 Unimplemented data memory location; read as ’0’. Note 1: Not a physical register. CFh D0h
Page 1 and 2: Devices Included in this Data Sheet
Page 3 and 4: 1.0 GENERAL DESCRIPTION The PIC16F8
Page 5 and 6: 2.0 PIC16F8X DEVICE VARIETIES A var
Page 7 and 8: 3.0 ARCHITECTURAL OVERVIEW The high
Page 9 and 10: TABLE 3-1 PIC16F8X PINOUT DESCRIPTI
Page 11: 4.0 MEMORY ORGANIZATION There are t
Page 15 and 16: 4.2.2.1 STATUS REGISTER The STATUS
Page 17 and 18: 4.2.2.3 INTCON REGISTER The INTCON
Page 19 and 20: 4.5 Indirect Addressing; INDF and F
Page 21 and 22: 5.0 I/O PORTS The PIC16F8X has two
Page 23 and 24: 5.2 PORTB and TRISB Registers PORTB
Page 25 and 26: 5.3 I/O Programming Considerations
Page 27 and 28: 6.0 TIMER0 MODULE AND TMR0 REGISTER
Page 29 and 30: 6.2 Using TMR0 with External Clock
Page 31 and 32: 6.3.1 SWITCHING PRESCALER ASSIGNMEN
Page 33 and 34: 7.0 DATA EEPROM MEMORY The EEPROM d
Page 35 and 36: 7.5 Write Verify Depending on the a
Page 37 and 38: 8.0 SPECIAL FEATURES OF THE CPU Wha
Page 39 and 40: FIGURE 8-2: CONFIGURATION WORD - PI
Page 41 and 42: FIGURE 8-6: EXTERNAL SERIES RESONAN
Page 43 and 44: PIC16F8X TABLE 8-3 RESET CONDITION
Page 45 and 46: PIC16F8X FIGURE 8-10: TIME-OUT SEQU
Page 47 and 48: 8.7 Time-out Sequence and Power-dow
Page 49 and 50: FIGURE 8-17: INT PIN INTERRUPT TIMI
Page 51 and 52: 8.11 Watchdog Timer (WDT) The Watch
Page 53 and 54: 8.12.3 WAKE-UP USING INTERRUPTS Whe
Page 55 and 56: 9.0 INSTRUCTION SET SUMMARY Each PI
Page 57 and 58: 9.1 Instruction Descriptions ADDLW
Page 59 and 60: BTFSS Bit Test f, Skip if Set Synta
Page 61 and 62: COMF Complement f Syntax: [ label ]
Page 63 and 64:
INCFSZ Increment f, Skip if 0 Synta
Page 65 and 66:
NOP No Operation Syntax: [ label ]
Page 67 and 68:
RLF Rotate Left f through Carry Syn
Page 69 and 70:
SUBWF Subtract W from f Syntax: [ l
Page 71 and 72:
10.0 DEVELOPMENT SUPPORT 10.1 Devel
Page 73 and 74:
MPASM has the following features to
Page 75 and 76:
PIC16F83/84 PIC16F8X 11.0 ELECTRICA
Page 77 and 78:
PIC16F83/84 PIC16F8X 11.1 DC CHARAC
Page 79 and 80:
PIC16F83/84 PIC16F8X 11.3 DC CHARAC
Page 81 and 82:
TABLE 11-2 TIMING PARAMETER SYMBOLO
Page 83 and 84:
FIGURE 11-4: CLKOUT AND I/O TIMING
Page 85 and 86:
FIGURE 11-6: TIMER0 CLOCK TIMINGS T
Page 87 and 88:
PIC16CR83/84 PIC16F8X 12.0 ELECTRIC
Page 89 and 90:
PIC16CR83/84 PIC16F8X 12.1 DC CHARA
Page 91 and 92:
PIC16CR83/84 PIC16F8X 12.3 DC CHARA
Page 93 and 94:
TABLE 12-2 TIMING PARAMETER SYMBOLO
Page 95 and 96:
FIGURE 12-4: CLKOUT AND I/O TIMING
Page 97 and 98:
FIGURE 12-6: TIMER0 CLOCK TIMINGS T
Page 99 and 100:
13.0 DC & AC CHARACTERISTICS GRAPHS
Page 101 and 102:
FIGURE 13-3: TYPICAL RC OSCILLATOR
Page 103 and 104:
FIGURE 13-8: VTH (INPUT THRESHOLD V
Page 105 and 106:
FIGURE 13-11: TYPICAL IDD vs. FREQU
Page 107 and 108:
FIGURE 13-13: WDT TIMER TIME-OUT PE
Page 109 and 110:
FIGURE 13-17: IOH vs. VOH, VDD = 3
Page 111 and 112:
14.0 PACKAGING INFORMATION 14.1 Pac
Page 113 and 114:
Package Type: K04-051 18-Lead Plast
Page 115 and 116:
APPENDIX A: FEATURE IMPROVEMENTS -
Page 117 and 118:
PIC16F8X APPENDIX E: CONVERSION CON
Page 119 and 120:
INDEX Numerics 8.1 Configuration Bi
Page 121 and 122:
ON-LINE SUPPORT Microchip provides
Page 123 and 124:
PIC16F8X PRODUCT IDENTIFICATION SYS
Page 125:
M AMERICAS Corporate Office 2355 We
show all

PIC16F8X, 18-Pin FLASH/EEPROM 8-Bit MCU Data Sheet - Microchip

Create successful ePaper yourself

Delete template?

Save as template?