PIC16F8X, 18-Pin FLASH/EEPROM 8-Bit MCU Data Sheet - Microchip

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PIC16F8X TABLE 4-1 REGISTER FILE SUMMARY Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-on Reset Value on all other resets (Note3) Bank 0 00h INDF Uses contents of FSR to address data memory (not a physical register) ---- ---- ---- ---- 01h TMR0 8-bit real-time clock/counter xxxx xxxx uuuu uuuu 02h PCL Low order 8 bits of the Program Counter (PC) 0000 0000 0000 0000 03h STATUS (2) IRP RP1 RP0 TO PD Z DC C 0001 1xxx 000q quuu 04h FSR Indirect data memory address pointer 0 xxxx xxxx uuuu uuuu 05h PORTA — — — RA4/T0CKI RA3 RA2 RA1 RA0 ---x xxxx ---u uuuu 06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0/INT xxxx xxxx uuuu uuuu 07h Unimplemented location, read as '0' ---- ---- ---- ---- 08h EEDATA EEPROM data register xxxx xxxx uuuu uuuu 09h EEADR EEPROM address register xxxx xxxx uuuu uuuu 0Ah PCLATH — — — Write buffer for upper 5 bits of the PC (1) ---0 0000 ---0 0000 0Bh Bank 1 INTCON GIE EEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 80h INDF Uses contents of FSR to address data memory (not a physical register) ---- ---- ---- ---- 81h OPTION_ REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 82h PCL Low order 8 bits of Program Counter (PC) 0000 0000 0000 0000 83h STATUS (2) IRP RP1 RP0 TO PD Z DC C 0001 1xxx 000q quuu 84h FSR Indirect data memory address pointer 0 xxxx xxxx uuuu uuuu 85h TRISA — — — PORTA data direction register ---1 1111 ---1 1111 86h TRISB PORTB data direction register 1111 1111 1111 1111 87h Unimplemented location, read as '0' ---- ---- ---- ---- 88h EECON1 — — — EEIF WRERR WREN WR RD ---0 x000 ---0 q000 89h EECON2 EEPROM control register 2 (not a physical register) ---- ---- ---- ---- 0Ah PCLATH — — — Write buffer for upper 5 bits of the PC (1) ---0 0000 ---0 0000 0Bh INTCON GIE EEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u Legend: x = unknown, u = unchanged. - = unimplemented read as ’0’, q = value depends on condition. Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a slave register for PC. The contents of PCLATH can be transferred to the upper byte of the program counter, but the contents of PC is never transferred to PCLATH. 2: The TO and PD status bits in the STATUS register are not affected by a MCLR reset. 3: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset. DS30430C-page 14 © 1998 Microchip Technology Inc.
4.2.2.1 STATUS REGISTER The STATUS register contains the arithmetic status of the ALU, the RESET status and the bank select bit for data memory. As with any register, the STATUS register can be the destination for any instruction. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. For example, CLRF STATUS will clear the upper-three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged). FIGURE 4-1: STATUS REGISTER (ADDRESS 03h, 83h) PIC16F8X Only the BCF, BSF, SWAPF and MOVWF instructions should be used to alter the STATUS register (Table 9-2) because these instructions do not affect any status bit. Note 1: The IRP and RP1 bits (STATUS) are not used by the PIC16F8X and should be programmed as cleared. Use of these bits as general purpose R/W bits is NOT recommended, since this may affect upward compatibility with future products. Note 2: The C and DC bits operate as a borrow and digit borrow out bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples. Note 3: When the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. The specified bit(s) will be updated according to device logic R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x IRP RP1 RP0 TO PD Z DC C R = Readable bit bit7 bit0 W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 7: IRP: Register Bank Select bit (used for indirect addressing) 0 = Bank 0, 1 (00h - FFh) 1 = Bank 2, 3 (100h - 1FFh) The IRP bit is not used by the PIC16F8X. IRP should be maintained clear. bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing) 00 = Bank 0 (00h - 7Fh) 01 = Bank 1 (80h - FFh) 10 = Bank 2 (100h - 17Fh) 11 = Bank 3 (180h - 1FFh) Each bank is 128 bytes. Only bit RP0 is used by the PIC16F8X. RP1 should be maintained clear. bit 4: TO: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred bit 3: PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 2: Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1: DC: Digit carry/borrow bit (for ADDWF and ADDLW instructions) (For borrow the polarity is reversed) 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result bit 0: C: Carry/borrow bit (for ADDWF and ADDLW instructions) 1 = A carry-out from the most significant bit of the result occurred 0 = No carry-out from the most significant bit of the result occurred Note:For borrow the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register. © 1998 Microchip Technology Inc. DS30430C-page 15
Page 1 and 2: Devices Included in this Data Sheet
Page 3 and 4: 1.0 GENERAL DESCRIPTION The PIC16F8
Page 5 and 6: 2.0 PIC16F8X DEVICE VARIETIES A var
Page 7 and 8: 3.0 ARCHITECTURAL OVERVIEW The high
Page 9 and 10: TABLE 3-1 PIC16F8X PINOUT DESCRIPTI
Page 11 and 12: 4.0 MEMORY ORGANIZATION There are t
Page 13: FIGURE 4-1: REGISTER FILE MAP - PIC
Page 17 and 18: 4.2.2.3 INTCON REGISTER The INTCON
Page 19 and 20: 4.5 Indirect Addressing; INDF and F
Page 21 and 22: 5.0 I/O PORTS The PIC16F8X has two
Page 23 and 24: 5.2 PORTB and TRISB Registers PORTB
Page 25 and 26: 5.3 I/O Programming Considerations
Page 27 and 28: 6.0 TIMER0 MODULE AND TMR0 REGISTER
Page 29 and 30: 6.2 Using TMR0 with External Clock
Page 31 and 32: 6.3.1 SWITCHING PRESCALER ASSIGNMEN
Page 33 and 34: 7.0 DATA EEPROM MEMORY The EEPROM d
Page 35 and 36: 7.5 Write Verify Depending on the a
Page 37 and 38: 8.0 SPECIAL FEATURES OF THE CPU Wha
Page 39 and 40: FIGURE 8-2: CONFIGURATION WORD - PI
Page 41 and 42: FIGURE 8-6: EXTERNAL SERIES RESONAN
Page 43 and 44: PIC16F8X TABLE 8-3 RESET CONDITION
Page 45 and 46: PIC16F8X FIGURE 8-10: TIME-OUT SEQU
Page 47 and 48: 8.7 Time-out Sequence and Power-dow
Page 49 and 50: FIGURE 8-17: INT PIN INTERRUPT TIMI
Page 51 and 52: 8.11 Watchdog Timer (WDT) The Watch
Page 53 and 54: 8.12.3 WAKE-UP USING INTERRUPTS Whe
Page 55 and 56: 9.0 INSTRUCTION SET SUMMARY Each PI
Page 57 and 58: 9.1 Instruction Descriptions ADDLW
Page 59 and 60: BTFSS Bit Test f, Skip if Set Synta
Page 61 and 62: COMF Complement f Syntax: [ label ]
Page 63 and 64: INCFSZ Increment f, Skip if 0 Synta
Page 65 and 66:
NOP No Operation Syntax: [ label ]
Page 67 and 68:
RLF Rotate Left f through Carry Syn
Page 69 and 70:
SUBWF Subtract W from f Syntax: [ l
Page 71 and 72:
10.0 DEVELOPMENT SUPPORT 10.1 Devel
Page 73 and 74:
MPASM has the following features to
Page 75 and 76:
PIC16F83/84 PIC16F8X 11.0 ELECTRICA
Page 77 and 78:
PIC16F83/84 PIC16F8X 11.1 DC CHARAC
Page 79 and 80:
PIC16F83/84 PIC16F8X 11.3 DC CHARAC
Page 81 and 82:
TABLE 11-2 TIMING PARAMETER SYMBOLO
Page 83 and 84:
FIGURE 11-4: CLKOUT AND I/O TIMING
Page 85 and 86:
FIGURE 11-6: TIMER0 CLOCK TIMINGS T
Page 87 and 88:
PIC16CR83/84 PIC16F8X 12.0 ELECTRIC
Page 89 and 90:
PIC16CR83/84 PIC16F8X 12.1 DC CHARA
Page 91 and 92:
PIC16CR83/84 PIC16F8X 12.3 DC CHARA
Page 93 and 94:
TABLE 12-2 TIMING PARAMETER SYMBOLO
Page 95 and 96:
FIGURE 12-4: CLKOUT AND I/O TIMING
Page 97 and 98:
FIGURE 12-6: TIMER0 CLOCK TIMINGS T
Page 99 and 100:
13.0 DC & AC CHARACTERISTICS GRAPHS
Page 101 and 102:
FIGURE 13-3: TYPICAL RC OSCILLATOR
Page 103 and 104:
FIGURE 13-8: VTH (INPUT THRESHOLD V
Page 105 and 106:
FIGURE 13-11: TYPICAL IDD vs. FREQU
Page 107 and 108:
FIGURE 13-13: WDT TIMER TIME-OUT PE
Page 109 and 110:
FIGURE 13-17: IOH vs. VOH, VDD = 3
Page 111 and 112:
14.0 PACKAGING INFORMATION 14.1 Pac
Page 113 and 114:
Package Type: K04-051 18-Lead Plast
Page 115 and 116:
APPENDIX A: FEATURE IMPROVEMENTS -
Page 117 and 118:
PIC16F8X APPENDIX E: CONVERSION CON
Page 119 and 120:
INDEX Numerics 8.1 Configuration Bi
Page 121 and 122:
ON-LINE SUPPORT Microchip provides
Page 123 and 124:
PIC16F8X PRODUCT IDENTIFICATION SYS
Page 125:
M AMERICAS Corporate Office 2355 We
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PIC16F8X, 18-Pin FLASH/EEPROM 8-Bit MCU Data Sheet - Microchip

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