Cortex-M0+ Devices Generic User Guide - Keil

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Introduction1.1 About the Cortex-M0+ processor and core peripheralsThe Cortex-M0+ processor is an entry-level 32-bit ARM Cortex processor designed for a broadrange of embedded applications. It offers significant benefits to developers, including:• a simple architecture that is easy to learn and program• ultra-low power, energy-efficient operation• excellent code density• deterministic, high-performance interrupt handling• upward compatibility with Cortex-M processor family• platform security robustness, with optional integrated Memory Protection Unit (MPU).Cortex-M0+ ComponentsInterruptsCortex-M0+ ProcessorNestedVectoredInterruptController(NVIC)Cortex-M0+processorcoreOptional DebugBreakpoint &WatchpointUnitsOptionalMicro TraceBuffer(MTB)OptionalWakeupInterruptController(WIC)OptionalMemoryProtectionUnit (MPU)Bus matrixDebuggerinterfaceOptionalDebugAccessPortAHB-Lite interfaceto systemOptionalsingle-cycleI/O portOptionalSerial-Wire or JTAGdebug portFigure 1-1 Cortex-M0+ implementationThe Cortex-M0+ processor is built on a highly area and power optimized 32-bit processor core,with a 2-stage pipeline von Neumann architecture. The processor delivers exceptional energyefficiency through a small but powerful instruction set and extensively optimized design,providing high-end processing hardware including either:• a single-cycle multiplier, in designs optimized for high performance• a 32-cycle multiplier, in designs optimized for low area.The Cortex-M0+ processor implements the ARMv6-M architecture, that is based on the 16-bitThumb ® instruction set and includes Thumb-2 technology. This provides the exceptionalperformance expected of a modern 32-bit architecture, with a higher code density than 8-bit and16-bit microcontrollers.The Cortex-M0+ processor closely integrates a configurable Nested Vectored InterruptController (NVIC), to deliver industry-leading interrupt performance. The NVIC:• includes a Non-Maskable Interrupt (NMI)• provides zero jitter interrupt option• provides four interrupt priority levels.ARM DUI 0662A Copyright © 2012 ARM. All rights reserved. 1-2ID041812Non-Confidential
IntroductionThe tight integration of the processor core and NVIC provides fast execution of InterruptService Routines (ISRs), dramatically reducing the interrupt latency. This is achieved throughthe hardware stacking of registers, and the ability to abandon and restart load-multiple andstore-multiple operations. Interrupt handlers do not require any assembler wrapper code,removing any code overhead from the ISRs. Tail-chaining optimization also significantlyreduces the overhead when switching from one ISR to another.To optimize low-power designs, the NVIC integrates with the sleep modes. Optionally, sleepmode support can include a deep sleep function that enables the entire device to be rapidlypowered down.1.1.1 System-level interfaceThe Cortex-M0+ processor provides a single system-level interface using AMBA ® technologyto provide high speed, low latency memory accesses.The Cortex-M0+ processor has an optional Memory Protection Unit (MPU) that provides finegrain memory control, enabling applications to use privilege levels, separating and protectingcode, data and stack on a task-by-task basis.1.1.2 Optional integrated configurable debugThe Cortex-M0+ processor can implement a complete hardware debug solution, with extensivehardware breakpoint and watchpoint options. This provides high system visibility of theprocessor, memory and peripherals through a JTAG port or a 2-pin Serial Wire Debug (SWD)port that is ideal for microcontrollers and other small package devices. The MCU vendordetermines the debug feature configuration and therefore this can differ across different devicesand families.1.1.3 Cortex-M0+ processor features summary• Thumb instruction set with Thumb-2 technology• high code density with 32-bit performance• optional Unprivileged and Privileged mode execution• tools and binary upwards compatible with Cortex-M processor family• integrated ultra low-power sleep modes• efficient code execution enabling slower processor clock or increasing sleep time• optional single-cycle 32-bit hardware multiplier• zero jitter interrupt handling• optional Memory Protection Unit (MPU) for safety-critical applications• optional single-cycle I/O port• optional Vector Table Offset Register (VTOR)• extensive debug capabilities.1.1.4 Cortex-M0+ core peripheralsThese are:NVICThe NVIC is an embedded interrupt controller that supports low latency interruptprocessing.System Control BlockThe System Control Block (SCB) is the programmers model interface to theprocessor. It provides system implementation information and system control,including configuration, control, and reporting of system exceptions.ARM DUI 0662A Copyright © 2012 ARM. All rights reserved. 1-3ID041812Non-Confidential
Page 1 and 2: Cortex-M0+ DevicesGeneric User Guid
Page 3: ContentsCortex-M0+ Devices Generic
Page 7 and 8: PrefaceTypographical ConventionsThe
Page 9: Chapter 1IntroductionThis chapter i
Page 13 and 14: Chapter 2The Cortex-M0+ ProcessorTh
Page 15 and 16: The Cortex-M0+ ProcessorIn Thread m
Page 17 and 18: The Cortex-M0+ ProcessorAccess thes
Page 19 and 20: The Cortex-M0+ ProcessorInterruptib
Page 21 and 22: The Cortex-M0+ Processor2.1.5 Data
Page 23 and 24: The Cortex-M0+ ProcessorThe differe
Page 25 and 26: The Cortex-M0+ ProcessorTable 2-10
Page 27 and 28: The Cortex-M0+ ProcessorLittle-endi
Page 29 and 30: The Cortex-M0+ ProcessorSysTickInte
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Page 33 and 34: The Cortex-M0+ ProcessorThe process
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Page 37 and 38: Chapter 3The Cortex-M0+ Instruction
Page 39 and 40: The Cortex-M0+ Instruction SetTable
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Chapter 4Cortex-M0+ PeripheralsThe
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Cortex-M0+ Peripherals4.2 Nested Ve
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Cortex-M0+ PeripheralsThe bit assig
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Cortex-M0+ Peripherals4.2.7 NVIC us
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Cortex-M0+ PeripheralsBits Name Fun
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Cortex-M0+ PeripheralsTable 4-11 IC
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Cortex-M0+ PeripheralsSystem Handle
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Cortex-M0+ PeripheralsTable 4-20 SY
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Cortex-M0+ PeripheralsTable 4-29 MP
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Cortex-M0+ Peripheralsbit controls
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Cortex-M0+ Devices Generic User Guide - Keil

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