Cortex-M0+ Devices Generic User Guide - Keil

The Cortex-M0+ Instruction Set3.2 Intrinsic functionsISO/IEC C code cannot directly access some Cortex-M0+ instructions. This section describesintrinsic functions that can generate these instructions, provided by CMSIS and that might beprovided by a C compiler. If a C compiler does not support an appropriate intrinsic function, youmight have to use inline assembler to access the relevant instruction.CMSIS provides the following intrinsic functions to generate instructions that ISO/IEC C codecannot directly access:Table 3-2 CMSIS intrinsic functions to generate some Cortex-M0+ instructionsInstructionCPSIE iCPSID iISBDSBDMBNOPREVREV16REVSHSEVWFEWFICMSIS intrinsic functionvoid __enable_irq(void)void __disable_irq(void)void __ISB(void)void __DSB(void)void __DMB(void)void __NOP(void)uint32_t __REV(uint32_t int value)uint32_t __REV16(uint32_t int value)uint32_t __REVSH(uint32_t int value)void __SEV(void)void __WFE(void)void __WFI(void)CMSIS also provides a number of functions for accessing the special registers using MRS and MSRinstructions:Table 3-3 CMSIS intrinsic functions to access the special registersSpecial register Access CMSIS functionPRIMASK Read uint32_t __get_PRIMASK (void)Writevoid __set_PRIMASK (uint32_t value)CONTROL Read uint32_t __get_CONTROL (void)Writevoid __set_CONTROL (uint32_t value)MSP Read uint32_t __get_MSP (void)Writevoid __set_MSP (uint32_t TopOfMainStack)PSP Read uint32_t __get_PSP (void)Writevoid __set_PSP (uint32_t TopOfProcStack)ARM DUI 0662A Copyright © 2012 ARM. All rights reserved. 3-5ID041812Non-Confidential