Cortex-M0+ Devices Generic User Guide - Keil

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The Cortex-M0+ Instruction Set3.5.4 CMP and CMNCompare and Compare Negative.SyntaxCMN Rn, RmCMP Rn, #immCMP Rn, Rmwhere:RnRmimmIs the register holding the first operand.Is the register to compare with.Is the immediate value to compare with.OperationThese instructions compare the value in a register with either the value in another register or animmediate value. They update the condition flags on the result, but do not write the result to aregister.The CMP instruction subtracts either the value in the register specified by Rm, or the immediateimm from the value in Rn and updates the flags. This is the same as a SUBS instruction, except thatthe result is discarded.The CMN instruction adds the value of Rm to the value in Rn and updates the flags. This is the sameas an ADDS instruction, except that the result is discarded.RestrictionsFor the:• CMN instruction Rn, and Rm must only specify R0-R7.• CMP instruction:— Rn and Rm can specify R0-R14— immediate must be in the range 0-255.Condition flagsThese instructions update the N, Z, C and V flags according to the result.ExamplesCMPCMNR2, R9R0, R2ARM DUI 0662A Copyright © 2012 ARM. All rights reserved. 3-26ID041812Non-Confidential
The Cortex-M0+ Instruction Set3.5.5 MOV and MVNMove and Move NOT.SyntaxMOV{S} Rd, RmMOVS Rd, #immMVNS Rd, Rmwhere:SRdRmIs an optional suffix. If S is specified, the condition code flags are updated on theresult of the operation, see Conditional execution on page 3-9.Is the destination register.Is a register.imm Is any value in the range 0-255.OperationThe MOV instruction copies the value of Rm into Rd.The MOVS instruction performs the same operation as the MOV instruction, but also updates the Nand Z flags.The MVNS instruction takes the value of Rm, performs a bitwise logical negate operation on thevalue, and places the result into Rd.RestrictionsIn these instructions, Rd, and Rm must only specify R0-R7.When Rd is the PC in a MOV instruction:• Bit[0] of the result is discarded.• A branch occurs to the address created by forcing bit[0] of the result to 0. The T-bitremains unmodified.NoteThough it is possible to use MOV as a branch instruction, ARM strongly recommends the use ofa BX or BLX instruction to branch for software portability.Condition flagsIf S is specified, these instructions:• update the N and Z flags according to the result• do not affect the C or V flags.ARM DUI 0662A Copyright © 2012 ARM. All rights reserved. 3-27ID041812Non-Confidential
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Cortex-M0+ DevicesGeneric User Guid
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ContentsCortex-M0+ Devices Generic
Page 7 and 8:
PrefaceTypographical ConventionsThe
Page 9 and 10:
Chapter 1IntroductionThis chapter i
Page 11 and 12: IntroductionThe tight integration o
Page 13 and 14: Chapter 2The Cortex-M0+ ProcessorTh
Page 15 and 16: The Cortex-M0+ ProcessorIn Thread m
Page 17 and 18: The Cortex-M0+ ProcessorAccess thes
Page 19 and 20: The Cortex-M0+ ProcessorInterruptib
Page 21 and 22: The Cortex-M0+ Processor2.1.5 Data
Page 23 and 24: The Cortex-M0+ ProcessorThe differe
Page 25 and 26: The Cortex-M0+ ProcessorTable 2-10
Page 27 and 28: The Cortex-M0+ ProcessorLittle-endi
Page 29 and 30: The Cortex-M0+ ProcessorSysTickInte
Page 31 and 32: The Cortex-M0+ ProcessorIf software
Page 33 and 34: The Cortex-M0+ ProcessorThe process
Page 35 and 36: The Cortex-M0+ Processor2.5 Power m
Page 37 and 38: Chapter 3The Cortex-M0+ Instruction
Page 39 and 40: The Cortex-M0+ Instruction SetTable
Page 41 and 42: The Cortex-M0+ Instruction Set3.2 I
Page 43 and 44: The Cortex-M0+ Instruction SetNote
Page 45 and 46: The Cortex-M0+ Instruction Set3.3.5
Page 47 and 48: The Cortex-M0+ Instruction Set3.4 M
Page 53 and 54: The Cortex-M0+ Instruction SetExamp
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Page 57 and 58: The Cortex-M0+ Instruction SetRestr
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Page 69 and 70: The Cortex-M0+ Instruction Set3.6 B
Page 71 and 72: The Cortex-M0+ Instruction SetCondi
Page 85 and 86: Chapter 4Cortex-M0+ PeripheralsThe
Page 87 and 88: Cortex-M0+ Peripherals4.2 Nested Ve
Page 89 and 90: Cortex-M0+ PeripheralsThe bit assig
Page 91 and 92: Cortex-M0+ Peripherals4.2.7 NVIC us
Page 93 and 94: Cortex-M0+ PeripheralsBits Name Fun
Page 95 and 96: Cortex-M0+ PeripheralsTable 4-11 IC
Page 97 and 98: Cortex-M0+ PeripheralsTable 4-13 AI
Page 99 and 100: Cortex-M0+ PeripheralsSystem Handle
Page 101 and 102: Cortex-M0+ PeripheralsTable 4-20 SY
Page 103 and 104: Cortex-M0+ Peripherals4.5 Memory Pr
Page 105 and 106: Cortex-M0+ PeripheralsSee the regis
Page 107 and 108: Cortex-M0+ PeripheralsTable 4-29 MP
Page 109 and 110: Cortex-M0+ PeripheralsThe smallest
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Cortex-M0+ Devices Generic User Guide - Keil

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