Cortex-M0+ Devices Generic User Guide - Keil

The Cortex-M0+ Instruction Set3.5.6 MULSMultiply using 32-bit operands, and producing a 32-bit result.SyntaxMULS Rd, Rn, Rmwhere:RdRn, RmIs the destination register.Are registers holding the values to be multiplied.OperationThe MUL instruction multiplies the values in the registers specified by Rn and Rm, and places theleast significant 32 bits of the result in Rd. The condition code flags are updated on the result ofthe operation, see Conditional execution on page 3-9.The results of this instruction do not depend on whether the operands are signed or unsigned.RestrictionsIn this instruction:• Rd, Rn, and Rm must only specify R0-R7• Rd must be the same as Rm.Condition flagsThis instruction:• updates the N and Z flags according to the result• does not affect the C or V flags.ExamplesMULS R0, R2, R0 ; Multiply with flag update, R0 = R0 x R2ARM DUI 0662A Copyright © 2012 ARM. All rights reserved. 3-29ID041812Non-Confidential