Cortex-M0+ Devices Generic User Guide - Keil

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The Cortex-M0+ ProcessorTable 2-2 Core register set summary (continued)Name Type a Reset value DescriptionEPSR RO Unknown b Execution Program Status Register on page 2-6PRIMASK RW 0x00000000 Priority Mask Register on page 2-7CONTROL RW 0x00000000 CONTROL register on page 2-8a. Describes access type during program execution in Thread mode and Handler mode. Debugaccess can differ.b. Bit[24] is the T-bit and is loaded from bit[0] of the reset vector.General-purpose registersR0-R12 are 32-bit general-purpose registers for data operations.Stack PointerThe Stack Pointer (SP) is register R13. In Thread mode, bit[1] of the CONTROL registerindicates the stack pointer to use:• 0 = Main Stack Pointer (MSP). This is the reset value.• 1 = Process Stack Pointer (PSP).On reset, the processor loads the MSP with the value from address 0x00000000.Link RegisterThe Link Register (LR) is register R14. It stores the return information for subroutines, functioncalls, and exceptions. On reset, the LR value is Unknown.Program CounterThe Program Counter (PC) is register R15. It contains the current program address. On reset,the processor loads the PC with the value of the reset vector, that is at address 0x00000004. Bit[0]of the value is loaded into the EPSR T-bit at reset and must be 1.Program Status RegisterThe Program Status Register (PSR) combines:• Application Program Status Register (APSR)• Interrupt Program Status Register (IPSR)• Execution Program Status Register (EPSR).These registers are mutually exclusive bitfields in the 32-bit PSR. The PSR bit assignments are:31 30 29 28 2725 24 23650APSRN Z C VReservedIPSRReservedException numberEPSR Reserved TReservedARM DUI 0662A Copyright © 2012 ARM. All rights reserved. 2-4ID041812Non-Confidential
The Cortex-M0+ ProcessorAccess these registers individually or as a combination of any two or all three registers, usingthe register name as an argument to the MSR or MRS instructions. For example:• read all of the registers using PSR with the MRS instruction• write to the APSR using APSR with the MSR instruction.The PSR combinations and attributes are:Table 2-3 PSR register combinationsRegister Type CombinationPSRRW a, bAPSR, EPSR, and IPSRIEPSR RO EPSR and IPSRIAPSR RW a APSR and IPSREAPSR RW b APSR and EPSRa. The processor ignores writes to the IPSRbits.b. Reads of the EPSR bits return zero, and theprocessor ignores writes to the these bitsSee the instruction descriptions MRS on page 3-42 and MSR on page 3-43 for more informationabout how to access the program status registers.Application Program Status RegisterThe APSR contains the current state of the condition flags, from previous instructionexecutions. See the register summary in Table 2-2 on page 2-3 for its attributes. The bitassignments are:Table 2-4 APSR bit assignmentsBits Name Function[31] N Negative flag[30] Z Zero flag[29] C Carry or borrow flag[28] V Overflow flag[27:0] - ReservedSee The condition flags on page 3-9 for more information about the APSR negative, zero, carryor borrow, and overflow flags.ARM DUI 0662A Copyright © 2012 ARM. All rights reserved. 2-5ID041812Non-Confidential
Page 1 and 2: Cortex-M0+ DevicesGeneric User Guid
Page 3: ContentsCortex-M0+ Devices Generic
Page 7 and 8: PrefaceTypographical ConventionsThe
Page 9 and 10: Chapter 1IntroductionThis chapter i
Page 11 and 12: IntroductionThe tight integration o
Page 13 and 14: Chapter 2The Cortex-M0+ ProcessorTh
Page 15: The Cortex-M0+ ProcessorIn Thread m
Page 19 and 20: The Cortex-M0+ ProcessorInterruptib
Page 21 and 22: The Cortex-M0+ Processor2.1.5 Data
Page 23 and 24: The Cortex-M0+ ProcessorThe differe
Page 25 and 26: The Cortex-M0+ ProcessorTable 2-10
Page 27 and 28: The Cortex-M0+ ProcessorLittle-endi
Page 29 and 30: The Cortex-M0+ ProcessorSysTickInte
Page 31 and 32: The Cortex-M0+ ProcessorIf software
Page 33 and 34: The Cortex-M0+ ProcessorThe process
Page 35 and 36: The Cortex-M0+ Processor2.5 Power m
Page 37 and 38: Chapter 3The Cortex-M0+ Instruction
Page 39 and 40: The Cortex-M0+ Instruction SetTable
Page 41 and 42: The Cortex-M0+ Instruction Set3.2 I
Page 43 and 44: The Cortex-M0+ Instruction SetNote
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Chapter 4Cortex-M0+ PeripheralsThe
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Cortex-M0+ Peripherals4.2 Nested Ve
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Cortex-M0+ PeripheralsThe bit assig
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Cortex-M0+ Peripherals4.2.7 NVIC us
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Cortex-M0+ PeripheralsBits Name Fun
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Cortex-M0+ PeripheralsTable 4-11 IC
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Cortex-M0+ PeripheralsSystem Handle
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Cortex-M0+ PeripheralsTable 4-20 SY
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Cortex-M0+ Devices Generic User Guide - Keil

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